1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* migration helpers, for KVM - will be removed in 2.6.25: */
8 #define Xgt_desc_struct desc_ptr
10 /* Forward declaration, a strange C thing */
15 #include <asm/math_emu.h>
16 #include <asm/segment.h>
17 #include <asm/types.h>
18 #include <asm/sigcontext.h>
19 #include <asm/current.h>
20 #include <asm/cpufeature.h>
21 #include <asm/system.h>
23 #include <asm/percpu.h>
25 #include <asm/desc_defs.h>
28 #include <linux/personality.h>
29 #include <linux/cpumask.h>
30 #include <linux/cache.h>
31 #include <linux/threads.h>
32 #include <linux/init.h>
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
38 static inline void *current_text_addr(void)
42 asm volatile("mov $1f, %0; 1:":"=r" (pc));
47 #ifdef CONFIG_X86_VSMP
48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
51 # define ARCH_MIN_TASKALIGN 16
52 # define ARCH_MIN_MMSTRUCT_ALIGN 0
56 * CPU type and hardware bug flags. Kept separately for each CPU.
57 * Members of this structure are referenced in head.S, so think twice
58 * before touching them. [mj]
62 __u8 x86; /* CPU family */
63 __u8 x86_vendor; /* CPU vendor */
67 char wp_works_ok; /* It doesn't on 386's */
69 /* Problems on some 486Dx4's and old 386's: */
78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
82 /* CPUID returned core id bits: */
84 /* Max extended CPUID function supported: */
85 __u32 extended_cpuid_level;
87 /* Maximum supported CPUID level, -1=no CPUID: */
89 __u32 x86_capability[NCAPINTS];
90 char x86_vendor_id[16];
91 char x86_model_id[64];
92 /* in KB - valid for CPUS which support this call: */
94 int x86_cache_alignment; /* In bytes */
96 unsigned long loops_per_jiffy;
98 /* cpus sharing the last level cache: */
99 cpumask_t llc_shared_map;
101 /* cpuid returned max cores value: */
104 u16 x86_clflush_size;
106 /* number of cores as seen by the OS: */
108 /* Physical processor id: */
112 /* Index into per_cpu list: */
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_NEXGEN 4
122 #define X86_VENDOR_CENTAUR 5
123 #define X86_VENDOR_TRANSMETA 7
124 #define X86_VENDOR_NSC 8
125 #define X86_VENDOR_NUM 9
127 #define X86_VENDOR_UNKNOWN 0xff
130 * capabilities of CPUs
132 extern struct cpuinfo_x86 boot_cpu_data;
133 extern struct cpuinfo_x86 new_cpu_data;
135 extern struct tss_struct doublefault_tss;
136 extern __u32 cleared_cpu_caps[NCAPINTS];
139 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
140 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
141 #define current_cpu_data cpu_data(smp_processor_id())
143 #define cpu_data(cpu) boot_cpu_data
144 #define current_cpu_data boot_cpu_data
147 static inline int hlt_works(int cpu)
150 return cpu_data(cpu).hlt_works_ok;
156 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
158 extern void cpu_detect(struct cpuinfo_x86 *c);
160 extern void identify_cpu(struct cpuinfo_x86 *);
161 extern void identify_boot_cpu(void);
162 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
163 extern void print_cpu_info(struct cpuinfo_x86 *);
164 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
165 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
166 extern unsigned short num_cache_leaves;
168 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
169 extern void detect_ht(struct cpuinfo_x86 *c);
171 static inline void detect_ht(struct cpuinfo_x86 *c) {}
174 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
175 unsigned int *ecx, unsigned int *edx)
177 /* ecx is often an input as well as an output. */
183 : "0" (*eax), "2" (*ecx));
186 static inline void load_cr3(pgd_t *pgdir)
188 write_cr3(__pa(pgdir));
192 /* This is the TSS defined by the hardware. */
194 unsigned short back_link, __blh;
196 unsigned short ss0, __ss0h;
198 /* ss1 caches MSR_IA32_SYSENTER_CS: */
199 unsigned short ss1, __ss1h;
201 unsigned short ss2, __ss2h;
213 unsigned short es, __esh;
214 unsigned short cs, __csh;
215 unsigned short ss, __ssh;
216 unsigned short ds, __dsh;
217 unsigned short fs, __fsh;
218 unsigned short gs, __gsh;
219 unsigned short ldt, __ldth;
220 unsigned short trace;
221 unsigned short io_bitmap_base;
223 } __attribute__((packed));
237 } __attribute__((packed)) ____cacheline_aligned;
243 #define IO_BITMAP_BITS 65536
244 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
245 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
246 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
247 #define INVALID_IO_BITMAP_OFFSET 0x8000
248 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
252 * The hardware state:
254 struct x86_hw_tss x86_tss;
257 * The extra 1 is there because the CPU will access an
258 * additional byte beyond the end of the IO permission
259 * bitmap. The extra byte must be all 1 bits, and must
260 * be within the limit.
262 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
264 * Cache the current maximum and the last task that used the bitmap:
266 unsigned long io_bitmap_max;
267 struct thread_struct *io_bitmap_owner;
270 * Pad the TSS to be cacheline-aligned (size is 0x100):
272 unsigned long __cacheline_filler[35];
274 * .. and then another 0x100 bytes for the emergency kernel stack:
276 unsigned long stack[64];
278 } __attribute__((packed));
280 DECLARE_PER_CPU(struct tss_struct, init_tss);
283 * Save the original ist values for checking stack pointers during debugging
286 unsigned long ist[7];
289 #define MXCSR_DEFAULT 0x1f80
291 struct i387_fsave_struct {
299 /* 8*10 bytes for each FP-reg = 80 bytes: */
301 /* Software status information: */
305 struct i387_fxsave_struct {
324 /* 8*16 bytes for each FP-reg = 128 bytes: */
326 /* 16*16 bytes for each XMM-reg = 256 bytes: */
330 } __attribute__((aligned(16)));
332 struct i387_soft_struct {
340 /* 8*10 bytes for each FP-reg = 80 bytes: */
353 struct i387_fsave_struct fsave;
354 struct i387_fxsave_struct fxsave;
355 struct i387_soft_struct soft;
359 DECLARE_PER_CPU(struct orig_ist, orig_ist);
362 extern void print_cpu_info(struct cpuinfo_x86 *);
363 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
364 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
365 extern unsigned short num_cache_leaves;
367 struct thread_struct {
368 /* Cached TLS descriptors: */
369 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
373 unsigned long sysenter_cs;
375 unsigned long usersp; /* Copy from PDA */
378 unsigned short fsindex;
379 unsigned short gsindex;
384 /* Hardware debugging registers: */
385 unsigned long debugreg0;
386 unsigned long debugreg1;
387 unsigned long debugreg2;
388 unsigned long debugreg3;
389 unsigned long debugreg6;
390 unsigned long debugreg7;
393 unsigned long trap_no;
394 unsigned long error_code;
395 /* Floating point info: */
396 union i387_union i387 __attribute__((aligned(16)));;
398 /* Virtual 86 mode info */
399 struct vm86_struct __user *vm86_info;
400 unsigned long screen_bitmap;
401 unsigned long v86flags;
402 unsigned long v86mask;
403 unsigned long saved_sp0;
404 unsigned int saved_fs;
405 unsigned int saved_gs;
407 /* IO permissions: */
408 unsigned long *io_bitmap_ptr;
410 /* Max allowed port in the bitmap, in bytes: */
411 unsigned io_bitmap_max;
412 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
413 unsigned long debugctlmsr;
414 /* Debug Store - if not 0 points to a DS Save Area configuration;
415 * goes into MSR_IA32_DS_AREA */
416 unsigned long ds_area_msr;
419 static inline unsigned long native_get_debugreg(int regno)
421 unsigned long val = 0; /* Damn you, gcc! */
425 asm("mov %%db0, %0" :"=r" (val)); break;
427 asm("mov %%db1, %0" :"=r" (val)); break;
429 asm("mov %%db2, %0" :"=r" (val)); break;
431 asm("mov %%db3, %0" :"=r" (val)); break;
433 asm("mov %%db6, %0" :"=r" (val)); break;
435 asm("mov %%db7, %0" :"=r" (val)); break;
442 static inline void native_set_debugreg(int regno, unsigned long value)
446 asm("mov %0, %%db0" ::"r" (value));
449 asm("mov %0, %%db1" ::"r" (value));
452 asm("mov %0, %%db2" ::"r" (value));
455 asm("mov %0, %%db3" ::"r" (value));
458 asm("mov %0, %%db6" ::"r" (value));
461 asm("mov %0, %%db7" ::"r" (value));
469 * Set IOPL bits in EFLAGS from given mask
471 static inline void native_set_iopl_mask(unsigned mask)
476 __asm__ __volatile__ ("pushfl;"
483 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
488 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
490 tss->x86_tss.sp0 = thread->sp0;
492 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
493 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
494 tss->x86_tss.ss1 = thread->sysenter_cs;
495 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
500 static inline void native_swapgs(void)
503 asm volatile("swapgs" ::: "memory");
507 #ifdef CONFIG_PARAVIRT
508 #include <asm/paravirt.h>
510 #define __cpuid native_cpuid
511 #define paravirt_enabled() 0
514 * These special macros can be used to get or set a debugging register
516 #define get_debugreg(var, register) \
517 (var) = native_get_debugreg(register)
518 #define set_debugreg(value, register) \
519 native_set_debugreg(register, value)
522 load_sp0(struct tss_struct *tss, struct thread_struct *thread)
524 native_load_sp0(tss, thread);
527 #define set_iopl_mask native_set_iopl_mask
528 #define SWAPGS swapgs
529 #endif /* CONFIG_PARAVIRT */
532 * Save the cr4 feature set we're using (ie
533 * Pentium 4MB enable and PPro Global page
534 * enable), so that any CPU's that boot up
535 * after us can get the correct flags.
537 extern unsigned long mmu_cr4_features;
539 static inline void set_in_cr4(unsigned long mask)
543 mmu_cr4_features |= mask;
549 static inline void clear_in_cr4(unsigned long mask)
553 mmu_cr4_features &= ~mask;
559 struct microcode_header {
567 unsigned int datasize;
568 unsigned int totalsize;
569 unsigned int reserved[3];
573 struct microcode_header hdr;
574 unsigned int bits[0];
577 typedef struct microcode microcode_t;
578 typedef struct microcode_header microcode_header_t;
580 /* microcode format is extended from prescott processors */
581 struct extended_signature {
587 struct extended_sigtable {
590 unsigned int reserved[3];
591 struct extended_signature sigs[0];
600 * create a kernel thread without removing it from tasklists
602 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
604 /* Free all resources held by a thread. */
605 extern void release_thread(struct task_struct *);
607 /* Prepare to copy thread state - unlazy all lazy state */
608 extern void prepare_to_copy(struct task_struct *tsk);
610 unsigned long get_wchan(struct task_struct *p);
613 * Generic CPUID function
614 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
615 * resulting in stale register contents being returned.
617 static inline void cpuid(unsigned int op,
618 unsigned int *eax, unsigned int *ebx,
619 unsigned int *ecx, unsigned int *edx)
623 __cpuid(eax, ebx, ecx, edx);
626 /* Some CPUID calls want 'count' to be placed in ecx */
627 static inline void cpuid_count(unsigned int op, int count,
628 unsigned int *eax, unsigned int *ebx,
629 unsigned int *ecx, unsigned int *edx)
633 __cpuid(eax, ebx, ecx, edx);
637 * CPUID functions returning a single datum
639 static inline unsigned int cpuid_eax(unsigned int op)
641 unsigned int eax, ebx, ecx, edx;
643 cpuid(op, &eax, &ebx, &ecx, &edx);
648 static inline unsigned int cpuid_ebx(unsigned int op)
650 unsigned int eax, ebx, ecx, edx;
652 cpuid(op, &eax, &ebx, &ecx, &edx);
657 static inline unsigned int cpuid_ecx(unsigned int op)
659 unsigned int eax, ebx, ecx, edx;
661 cpuid(op, &eax, &ebx, &ecx, &edx);
666 static inline unsigned int cpuid_edx(unsigned int op)
668 unsigned int eax, ebx, ecx, edx;
670 cpuid(op, &eax, &ebx, &ecx, &edx);
675 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
676 static inline void rep_nop(void)
678 __asm__ __volatile__("rep; nop" ::: "memory");
681 static inline void cpu_relax(void)
686 /* Stop speculative execution: */
687 static inline void sync_core(void)
691 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
692 : "ebx", "ecx", "edx", "memory");
696 __monitor(const void *eax, unsigned long ecx, unsigned long edx)
698 /* "monitor %eax, %ecx, %edx;" */
700 ".byte 0x0f, 0x01, 0xc8;"
701 :: "a" (eax), "c" (ecx), "d"(edx));
704 static inline void __mwait(unsigned long eax, unsigned long ecx)
706 /* "mwait %eax, %ecx;" */
708 ".byte 0x0f, 0x01, 0xc9;"
709 :: "a" (eax), "c" (ecx));
712 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
714 /* "mwait %eax, %ecx;" */
716 "sti; .byte 0x0f, 0x01, 0xc9;"
717 :: "a" (eax), "c" (ecx));
720 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
722 extern int force_mwait;
724 extern void select_idle_routine(const struct cpuinfo_x86 *c);
726 extern unsigned long boot_option_idle_override;
728 extern void enable_sep_cpu(void);
729 extern int sysenter_setup(void);
731 /* Defined in head.S */
732 extern struct desc_ptr early_gdt_descr;
734 extern void cpu_set_gdt(int);
735 extern void switch_to_new_gdt(void);
736 extern void cpu_init(void);
737 extern void init_gdt(int cpu);
740 * from system description table in BIOS. Mostly for MCA use, but
741 * others may find it useful:
743 extern unsigned int machine_id;
744 extern unsigned int machine_submodel_id;
745 extern unsigned int BIOS_revision;
747 /* Boot loader type from the setup header: */
748 extern int bootloader_type;
750 extern char ignore_fpu_irq;
752 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
753 #define ARCH_HAS_PREFETCHW
754 #define ARCH_HAS_SPINLOCK_PREFETCH
757 # define BASE_PREFETCH ASM_NOP4
758 # define ARCH_HAS_PREFETCH
760 # define BASE_PREFETCH "prefetcht0 (%1)"
764 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
766 * It's not worth to care about 3dnow prefetches for the K6
767 * because they are microcoded there and very slow.
769 static inline void prefetch(const void *x)
771 alternative_input(BASE_PREFETCH,
778 * 3dnow prefetch to get an exclusive cache line.
779 * Useful for spinlocks to avoid one state transition in the
780 * cache coherency protocol:
782 static inline void prefetchw(const void *x)
784 alternative_input(BASE_PREFETCH,
790 static inline void spin_lock_prefetch(const void *x)
797 * User space process size: 3GB (default).
799 #define TASK_SIZE PAGE_OFFSET
800 #define STACK_TOP TASK_SIZE
801 #define STACK_TOP_MAX STACK_TOP
803 #define INIT_THREAD { \
804 .sp0 = sizeof(init_stack) + (long)&init_stack, \
806 .sysenter_cs = __KERNEL_CS, \
807 .io_bitmap_ptr = NULL, \
808 .fs = __KERNEL_PERCPU, \
812 * Note that the .io_bitmap member must be extra-big. This is because
813 * the CPU will access an additional byte beyond the end of the IO
814 * permission bitmap. The extra byte must be all 1 bits, and must
815 * be within the limit.
819 .sp0 = sizeof(init_stack) + (long)&init_stack, \
820 .ss0 = __KERNEL_DS, \
821 .ss1 = __KERNEL_CS, \
822 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
824 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
827 extern unsigned long thread_saved_pc(struct task_struct *tsk);
829 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
830 #define KSTK_TOP(info) \
832 unsigned long *__ptr = (unsigned long *)(info); \
833 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
837 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
838 * This is necessary to guarantee that the entire "struct pt_regs"
839 * is accessable even if the CPU haven't stored the SS/ESP registers
840 * on the stack (interrupt gate does not save these registers
841 * when switching to the same priv ring).
842 * Therefore beware: accessing the ss/esp fields of the
843 * "struct pt_regs" is possible, but they may contain the
844 * completely wrong values.
846 #define task_pt_regs(task) \
848 struct pt_regs *__regs__; \
849 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
853 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
857 * User space process size. 47bits minus one guard page.
859 #define TASK_SIZE64 (0x800000000000UL - 4096)
861 /* This decides where the kernel will search for a free chunk of vm
862 * space during mmap's.
864 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
865 0xc0000000 : 0xFFFFe000)
867 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
868 IA32_PAGE_OFFSET : TASK_SIZE64)
869 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
870 IA32_PAGE_OFFSET : TASK_SIZE64)
872 #define STACK_TOP TASK_SIZE
873 #define STACK_TOP_MAX TASK_SIZE64
875 #define INIT_THREAD { \
876 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
880 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
884 * Return saved PC of a blocked thread.
885 * What is this good for? it will be always the scheduler or ret_from_fork.
887 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
889 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
890 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
891 #endif /* CONFIG_X86_64 */
893 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
894 unsigned long new_sp);
897 * This decides where the kernel will search for a free chunk of vm
898 * space during mmap's.
900 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
902 #define KSTK_EIP(task) (task_pt_regs(task)->ip)