1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* migration helper, for KVM - will be removed in 2.6.25: */
7 #define Xgt_desc_struct desc_ptr
9 /* Forward declaration, a strange C thing */
14 #include <asm/math_emu.h>
15 #include <asm/segment.h>
16 #include <asm/types.h>
17 #include <asm/sigcontext.h>
18 #include <asm/current.h>
19 #include <asm/cpufeature.h>
20 #include <asm/system.h>
22 #include <asm/percpu.h>
24 #include <asm/desc_defs.h>
27 #include <linux/personality.h>
28 #include <linux/cpumask.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/init.h>
34 * Default implementation of macro that returns current
35 * instruction pointer ("program counter").
37 static inline void *current_text_addr(void)
41 asm volatile("mov $1f, %0; 1:":"=r" (pc));
46 #ifdef CONFIG_X86_VSMP
47 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
48 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
50 # define ARCH_MIN_TASKALIGN 16
51 # define ARCH_MIN_MMSTRUCT_ALIGN 0
55 * CPU type and hardware bug flags. Kept separately for each CPU.
56 * Members of this structure are referenced in head.S, so think twice
57 * before touching them. [mj]
61 __u8 x86; /* CPU family */
62 __u8 x86_vendor; /* CPU vendor */
66 char wp_works_ok; /* It doesn't on 386's */
68 /* Problems on some 486Dx4's and old 386's: */
77 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
81 /* CPUID returned core id bits: */
83 /* Max extended CPUID function supported: */
84 __u32 extended_cpuid_level;
86 /* Maximum supported CPUID level, -1=no CPUID: */
88 __u32 x86_capability[NCAPINTS];
89 char x86_vendor_id[16];
90 char x86_model_id[64];
91 /* in KB - valid for CPUS which support this call: */
93 int x86_cache_alignment; /* In bytes */
95 unsigned long loops_per_jiffy;
97 /* cpus sharing the last level cache: */
98 cpumask_t llc_shared_map;
100 /* cpuid returned max cores value: */
104 u16 x86_clflush_size;
106 /* number of cores as seen by the OS: */
108 /* Physical processor id: */
112 /* Index into per_cpu list: */
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_NEXGEN 4
122 #define X86_VENDOR_CENTAUR 5
123 #define X86_VENDOR_TRANSMETA 7
124 #define X86_VENDOR_NSC 8
125 #define X86_VENDOR_NUM 9
127 #define X86_VENDOR_UNKNOWN 0xff
130 * capabilities of CPUs
132 extern struct cpuinfo_x86 boot_cpu_data;
133 extern struct cpuinfo_x86 new_cpu_data;
135 extern struct tss_struct doublefault_tss;
136 extern __u32 cleared_cpu_caps[NCAPINTS];
139 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
140 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
141 #define current_cpu_data cpu_data(smp_processor_id())
143 #define cpu_data(cpu) boot_cpu_data
144 #define current_cpu_data boot_cpu_data
147 static inline int hlt_works(int cpu)
150 return cpu_data(cpu).hlt_works_ok;
156 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
158 extern void cpu_detect(struct cpuinfo_x86 *c);
160 extern void identify_cpu(struct cpuinfo_x86 *);
161 extern void identify_boot_cpu(void);
162 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
163 extern void print_cpu_info(struct cpuinfo_x86 *);
164 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
165 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
166 extern unsigned short num_cache_leaves;
168 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
169 extern void detect_ht(struct cpuinfo_x86 *c);
171 static inline void detect_ht(struct cpuinfo_x86 *c) {}
174 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
175 unsigned int *ecx, unsigned int *edx)
177 /* ecx is often an input as well as an output. */
183 : "0" (*eax), "2" (*ecx));
186 static inline void load_cr3(pgd_t *pgdir)
188 write_cr3(__pa(pgdir));
192 /* This is the TSS defined by the hardware. */
194 unsigned short back_link, __blh;
196 unsigned short ss0, __ss0h;
198 /* ss1 caches MSR_IA32_SYSENTER_CS: */
199 unsigned short ss1, __ss1h;
201 unsigned short ss2, __ss2h;
213 unsigned short es, __esh;
214 unsigned short cs, __csh;
215 unsigned short ss, __ssh;
216 unsigned short ds, __dsh;
217 unsigned short fs, __fsh;
218 unsigned short gs, __gsh;
219 unsigned short ldt, __ldth;
220 unsigned short trace;
221 unsigned short io_bitmap_base;
223 } __attribute__((packed));
237 } __attribute__((packed)) ____cacheline_aligned;
243 #define IO_BITMAP_BITS 65536
244 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
245 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
246 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
247 #define INVALID_IO_BITMAP_OFFSET 0x8000
248 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
252 * The hardware state:
254 struct x86_hw_tss x86_tss;
257 * The extra 1 is there because the CPU will access an
258 * additional byte beyond the end of the IO permission
259 * bitmap. The extra byte must be all 1 bits, and must
260 * be within the limit.
262 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
264 * Cache the current maximum and the last task that used the bitmap:
266 unsigned long io_bitmap_max;
267 struct thread_struct *io_bitmap_owner;
270 * Pad the TSS to be cacheline-aligned (size is 0x100):
272 unsigned long __cacheline_filler[35];
274 * .. and then another 0x100 bytes for the emergency kernel stack:
276 unsigned long stack[64];
278 } __attribute__((packed));
280 DECLARE_PER_CPU(struct tss_struct, init_tss);
283 * Save the original ist values for checking stack pointers during debugging
286 unsigned long ist[7];
289 #define MXCSR_DEFAULT 0x1f80
291 struct i387_fsave_struct {
292 u32 cwd; /* FPU Control Word */
293 u32 swd; /* FPU Status Word */
294 u32 twd; /* FPU Tag Word */
295 u32 fip; /* FPU IP Offset */
296 u32 fcs; /* FPU IP Selector */
297 u32 foo; /* FPU Operand Pointer Offset */
298 u32 fos; /* FPU Operand Pointer Selector */
300 /* 8*10 bytes for each FP-reg = 80 bytes: */
303 /* Software status information [not touched by FSAVE ]: */
307 struct i387_fxsave_struct {
308 u16 cwd; /* Control Word */
309 u16 swd; /* Status Word */
310 u16 twd; /* Tag Word */
311 u16 fop; /* Last Instruction Opcode */
314 u64 rip; /* Instruction Pointer */
315 u64 rdp; /* Data Pointer */
318 u32 fip; /* FPU IP Offset */
319 u32 fcs; /* FPU IP Selector */
320 u32 foo; /* FPU Operand Offset */
321 u32 fos; /* FPU Operand Selector */
324 u32 mxcsr; /* MXCSR Register State */
325 u32 mxcsr_mask; /* MXCSR Mask */
327 /* 8*16 bytes for each FP-reg = 128 bytes: */
330 /* 16*16 bytes for each XMM-reg = 256 bytes: */
335 } __attribute__((aligned(16)));
337 struct i387_soft_struct {
345 /* 8*10 bytes for each FP-reg = 80 bytes: */
357 union thread_xstate {
358 struct i387_fsave_struct fsave;
359 struct i387_fxsave_struct fxsave;
360 struct i387_soft_struct soft;
364 DECLARE_PER_CPU(struct orig_ist, orig_ist);
367 extern void print_cpu_info(struct cpuinfo_x86 *);
368 extern unsigned int xstate_size;
369 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
370 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
371 extern unsigned short num_cache_leaves;
373 struct thread_struct {
374 /* Cached TLS descriptors: */
375 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
379 unsigned long sysenter_cs;
381 unsigned long usersp; /* Copy from PDA */
384 unsigned short fsindex;
385 unsigned short gsindex;
390 /* Hardware debugging registers: */
391 unsigned long debugreg0;
392 unsigned long debugreg1;
393 unsigned long debugreg2;
394 unsigned long debugreg3;
395 unsigned long debugreg6;
396 unsigned long debugreg7;
399 unsigned long trap_no;
400 unsigned long error_code;
401 /* floating point and extended processor state */
402 union thread_xstate *xstate;
404 /* Virtual 86 mode info */
405 struct vm86_struct __user *vm86_info;
406 unsigned long screen_bitmap;
407 unsigned long v86flags;
408 unsigned long v86mask;
409 unsigned long saved_sp0;
410 unsigned int saved_fs;
411 unsigned int saved_gs;
413 /* IO permissions: */
414 unsigned long *io_bitmap_ptr;
416 /* Max allowed port in the bitmap, in bytes: */
417 unsigned io_bitmap_max;
418 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
419 unsigned long debugctlmsr;
420 /* Debug Store - if not 0 points to a DS Save Area configuration;
421 * goes into MSR_IA32_DS_AREA */
422 unsigned long ds_area_msr;
425 static inline unsigned long native_get_debugreg(int regno)
427 unsigned long val = 0; /* Damn you, gcc! */
431 asm("mov %%db0, %0" :"=r" (val));
434 asm("mov %%db1, %0" :"=r" (val));
437 asm("mov %%db2, %0" :"=r" (val));
440 asm("mov %%db3, %0" :"=r" (val));
443 asm("mov %%db6, %0" :"=r" (val));
446 asm("mov %%db7, %0" :"=r" (val));
454 static inline void native_set_debugreg(int regno, unsigned long value)
458 asm("mov %0, %%db0" ::"r" (value));
461 asm("mov %0, %%db1" ::"r" (value));
464 asm("mov %0, %%db2" ::"r" (value));
467 asm("mov %0, %%db3" ::"r" (value));
470 asm("mov %0, %%db6" ::"r" (value));
473 asm("mov %0, %%db7" ::"r" (value));
481 * Set IOPL bits in EFLAGS from given mask
483 static inline void native_set_iopl_mask(unsigned mask)
488 asm volatile ("pushfl;"
495 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
500 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
502 tss->x86_tss.sp0 = thread->sp0;
504 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
505 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
506 tss->x86_tss.ss1 = thread->sysenter_cs;
507 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
512 static inline void native_swapgs(void)
515 asm volatile("swapgs" ::: "memory");
519 #ifdef CONFIG_PARAVIRT
520 #include <asm/paravirt.h>
522 #define __cpuid native_cpuid
523 #define paravirt_enabled() 0
526 * These special macros can be used to get or set a debugging register
528 #define get_debugreg(var, register) \
529 (var) = native_get_debugreg(register)
530 #define set_debugreg(value, register) \
531 native_set_debugreg(register, value)
533 static inline void load_sp0(struct tss_struct *tss,
534 struct thread_struct *thread)
536 native_load_sp0(tss, thread);
539 #define set_iopl_mask native_set_iopl_mask
540 #define SWAPGS swapgs
541 #endif /* CONFIG_PARAVIRT */
544 * Save the cr4 feature set we're using (ie
545 * Pentium 4MB enable and PPro Global page
546 * enable), so that any CPU's that boot up
547 * after us can get the correct flags.
549 extern unsigned long mmu_cr4_features;
551 static inline void set_in_cr4(unsigned long mask)
555 mmu_cr4_features |= mask;
561 static inline void clear_in_cr4(unsigned long mask)
565 mmu_cr4_features &= ~mask;
571 struct microcode_header {
579 unsigned int datasize;
580 unsigned int totalsize;
581 unsigned int reserved[3];
585 struct microcode_header hdr;
586 unsigned int bits[0];
589 typedef struct microcode microcode_t;
590 typedef struct microcode_header microcode_header_t;
592 /* microcode format is extended from prescott processors */
593 struct extended_signature {
599 struct extended_sigtable {
602 unsigned int reserved[3];
603 struct extended_signature sigs[0];
612 * create a kernel thread without removing it from tasklists
614 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
616 /* Free all resources held by a thread. */
617 extern void release_thread(struct task_struct *);
619 /* Prepare to copy thread state - unlazy all lazy state */
620 extern void prepare_to_copy(struct task_struct *tsk);
622 unsigned long get_wchan(struct task_struct *p);
625 * Generic CPUID function
626 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
627 * resulting in stale register contents being returned.
629 static inline void cpuid(unsigned int op,
630 unsigned int *eax, unsigned int *ebx,
631 unsigned int *ecx, unsigned int *edx)
635 __cpuid(eax, ebx, ecx, edx);
638 /* Some CPUID calls want 'count' to be placed in ecx */
639 static inline void cpuid_count(unsigned int op, int count,
640 unsigned int *eax, unsigned int *ebx,
641 unsigned int *ecx, unsigned int *edx)
645 __cpuid(eax, ebx, ecx, edx);
649 * CPUID functions returning a single datum
651 static inline unsigned int cpuid_eax(unsigned int op)
653 unsigned int eax, ebx, ecx, edx;
655 cpuid(op, &eax, &ebx, &ecx, &edx);
660 static inline unsigned int cpuid_ebx(unsigned int op)
662 unsigned int eax, ebx, ecx, edx;
664 cpuid(op, &eax, &ebx, &ecx, &edx);
669 static inline unsigned int cpuid_ecx(unsigned int op)
671 unsigned int eax, ebx, ecx, edx;
673 cpuid(op, &eax, &ebx, &ecx, &edx);
678 static inline unsigned int cpuid_edx(unsigned int op)
680 unsigned int eax, ebx, ecx, edx;
682 cpuid(op, &eax, &ebx, &ecx, &edx);
687 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
688 static inline void rep_nop(void)
690 asm volatile("rep; nop" ::: "memory");
693 static inline void cpu_relax(void)
698 /* Stop speculative execution: */
699 static inline void sync_core(void)
703 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
704 : "ebx", "ecx", "edx", "memory");
707 static inline void __monitor(const void *eax, unsigned long ecx,
710 /* "monitor %eax, %ecx, %edx;" */
711 asm volatile(".byte 0x0f, 0x01, 0xc8;"
712 :: "a" (eax), "c" (ecx), "d"(edx));
715 static inline void __mwait(unsigned long eax, unsigned long ecx)
717 /* "mwait %eax, %ecx;" */
718 asm volatile(".byte 0x0f, 0x01, 0xc9;"
719 :: "a" (eax), "c" (ecx));
722 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
724 /* "mwait %eax, %ecx;" */
725 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
726 :: "a" (eax), "c" (ecx));
729 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
731 extern int force_mwait;
733 extern void select_idle_routine(const struct cpuinfo_x86 *c);
735 extern unsigned long boot_option_idle_override;
737 extern void enable_sep_cpu(void);
738 extern int sysenter_setup(void);
740 /* Defined in head.S */
741 extern struct desc_ptr early_gdt_descr;
743 extern void cpu_set_gdt(int);
744 extern void switch_to_new_gdt(void);
745 extern void cpu_init(void);
746 extern void init_gdt(int cpu);
748 static inline void update_debugctlmsr(unsigned long debugctlmsr)
750 #ifndef CONFIG_X86_DEBUGCTLMSR
751 if (boot_cpu_data.x86 < 6)
754 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
758 * from system description table in BIOS. Mostly for MCA use, but
759 * others may find it useful:
761 extern unsigned int machine_id;
762 extern unsigned int machine_submodel_id;
763 extern unsigned int BIOS_revision;
765 /* Boot loader type from the setup header: */
766 extern int bootloader_type;
768 extern char ignore_fpu_irq;
770 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
771 #define ARCH_HAS_PREFETCHW
772 #define ARCH_HAS_SPINLOCK_PREFETCH
775 # define BASE_PREFETCH ASM_NOP4
776 # define ARCH_HAS_PREFETCH
778 # define BASE_PREFETCH "prefetcht0 (%1)"
782 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
784 * It's not worth to care about 3dnow prefetches for the K6
785 * because they are microcoded there and very slow.
787 static inline void prefetch(const void *x)
789 alternative_input(BASE_PREFETCH,
796 * 3dnow prefetch to get an exclusive cache line.
797 * Useful for spinlocks to avoid one state transition in the
798 * cache coherency protocol:
800 static inline void prefetchw(const void *x)
802 alternative_input(BASE_PREFETCH,
808 static inline void spin_lock_prefetch(const void *x)
815 * User space process size: 3GB (default).
817 #define TASK_SIZE PAGE_OFFSET
818 #define STACK_TOP TASK_SIZE
819 #define STACK_TOP_MAX STACK_TOP
821 #define INIT_THREAD { \
822 .sp0 = sizeof(init_stack) + (long)&init_stack, \
824 .sysenter_cs = __KERNEL_CS, \
825 .io_bitmap_ptr = NULL, \
826 .fs = __KERNEL_PERCPU, \
830 * Note that the .io_bitmap member must be extra-big. This is because
831 * the CPU will access an additional byte beyond the end of the IO
832 * permission bitmap. The extra byte must be all 1 bits, and must
833 * be within the limit.
837 .sp0 = sizeof(init_stack) + (long)&init_stack, \
838 .ss0 = __KERNEL_DS, \
839 .ss1 = __KERNEL_CS, \
840 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
842 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
845 extern unsigned long thread_saved_pc(struct task_struct *tsk);
847 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
848 #define KSTK_TOP(info) \
850 unsigned long *__ptr = (unsigned long *)(info); \
851 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
855 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
856 * This is necessary to guarantee that the entire "struct pt_regs"
857 * is accessable even if the CPU haven't stored the SS/ESP registers
858 * on the stack (interrupt gate does not save these registers
859 * when switching to the same priv ring).
860 * Therefore beware: accessing the ss/esp fields of the
861 * "struct pt_regs" is possible, but they may contain the
862 * completely wrong values.
864 #define task_pt_regs(task) \
866 struct pt_regs *__regs__; \
867 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
871 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
875 * User space process size. 47bits minus one guard page.
877 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
879 /* This decides where the kernel will search for a free chunk of vm
880 * space during mmap's.
882 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
883 0xc0000000 : 0xFFFFe000)
885 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
886 IA32_PAGE_OFFSET : TASK_SIZE64)
887 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
888 IA32_PAGE_OFFSET : TASK_SIZE64)
890 #define STACK_TOP TASK_SIZE
891 #define STACK_TOP_MAX TASK_SIZE64
893 #define INIT_THREAD { \
894 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
898 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
902 * Return saved PC of a blocked thread.
903 * What is this good for? it will be always the scheduler or ret_from_fork.
905 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
907 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
908 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
909 #endif /* CONFIG_X86_64 */
911 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
912 unsigned long new_sp);
915 * This decides where the kernel will search for a free chunk of vm
916 * space during mmap's.
918 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
920 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
922 /* Get/set a process' ability to use the timestamp counter instruction */
923 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
924 #define SET_TSC_CTL(val) set_tsc_mode((val))
926 extern int get_tsc_mode(unsigned long adr);
927 extern int set_tsc_mode(unsigned int val);