1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* migration helper, for KVM - will be removed in 2.6.25: */
7 #define Xgt_desc_struct desc_ptr
9 /* Forward declaration, a strange C thing */
14 #include <asm/math_emu.h>
15 #include <asm/segment.h>
16 #include <asm/types.h>
17 #include <asm/sigcontext.h>
18 #include <asm/current.h>
19 #include <asm/cpufeature.h>
20 #include <asm/system.h>
22 #include <asm/percpu.h>
24 #include <asm/desc_defs.h>
27 #include <linux/personality.h>
28 #include <linux/cpumask.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/init.h>
34 * Default implementation of macro that returns current
35 * instruction pointer ("program counter").
37 static inline void *current_text_addr(void)
41 asm volatile("mov $1f, %0; 1:":"=r" (pc));
46 #ifdef CONFIG_X86_VSMP
47 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
48 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
50 # define ARCH_MIN_TASKALIGN 16
51 # define ARCH_MIN_MMSTRUCT_ALIGN 0
55 * CPU type and hardware bug flags. Kept separately for each CPU.
56 * Members of this structure are referenced in head.S, so think twice
57 * before touching them. [mj]
61 __u8 x86; /* CPU family */
62 __u8 x86_vendor; /* CPU vendor */
66 char wp_works_ok; /* It doesn't on 386's */
68 /* Problems on some 486Dx4's and old 386's: */
77 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
81 /* CPUID returned core id bits: */
83 /* Max extended CPUID function supported: */
84 __u32 extended_cpuid_level;
86 /* Maximum supported CPUID level, -1=no CPUID: */
88 __u32 x86_capability[NCAPINTS];
89 char x86_vendor_id[16];
90 char x86_model_id[64];
91 /* in KB - valid for CPUS which support this call: */
93 int x86_cache_alignment; /* In bytes */
95 unsigned long loops_per_jiffy;
97 /* cpus sharing the last level cache: */
98 cpumask_t llc_shared_map;
100 /* cpuid returned max cores value: */
104 u16 x86_clflush_size;
106 /* number of cores as seen by the OS: */
108 /* Physical processor id: */
112 /* Index into per_cpu list: */
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_CENTAUR 5
122 #define X86_VENDOR_TRANSMETA 7
123 #define X86_VENDOR_NSC 8
124 #define X86_VENDOR_NUM 9
126 #define X86_VENDOR_UNKNOWN 0xff
129 * capabilities of CPUs
131 extern struct cpuinfo_x86 boot_cpu_data;
132 extern struct cpuinfo_x86 new_cpu_data;
134 extern struct tss_struct doublefault_tss;
135 extern __u32 cleared_cpu_caps[NCAPINTS];
138 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
139 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
140 #define current_cpu_data cpu_data(smp_processor_id())
142 #define cpu_data(cpu) boot_cpu_data
143 #define current_cpu_data boot_cpu_data
146 static inline int hlt_works(int cpu)
149 return cpu_data(cpu).hlt_works_ok;
155 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
157 extern void cpu_detect(struct cpuinfo_x86 *c);
159 extern void identify_cpu(struct cpuinfo_x86 *);
160 extern void identify_boot_cpu(void);
161 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
162 extern void print_cpu_info(struct cpuinfo_x86 *);
163 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
164 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
165 extern unsigned short num_cache_leaves;
167 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
168 extern void detect_ht(struct cpuinfo_x86 *c);
170 static inline void detect_ht(struct cpuinfo_x86 *c) {}
173 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
174 unsigned int *ecx, unsigned int *edx)
176 /* ecx is often an input as well as an output. */
182 : "0" (*eax), "2" (*ecx));
185 static inline void load_cr3(pgd_t *pgdir)
187 write_cr3(__pa(pgdir));
191 /* This is the TSS defined by the hardware. */
193 unsigned short back_link, __blh;
195 unsigned short ss0, __ss0h;
197 /* ss1 caches MSR_IA32_SYSENTER_CS: */
198 unsigned short ss1, __ss1h;
200 unsigned short ss2, __ss2h;
212 unsigned short es, __esh;
213 unsigned short cs, __csh;
214 unsigned short ss, __ssh;
215 unsigned short ds, __dsh;
216 unsigned short fs, __fsh;
217 unsigned short gs, __gsh;
218 unsigned short ldt, __ldth;
219 unsigned short trace;
220 unsigned short io_bitmap_base;
222 } __attribute__((packed));
236 } __attribute__((packed)) ____cacheline_aligned;
242 #define IO_BITMAP_BITS 65536
243 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
244 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
245 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
246 #define INVALID_IO_BITMAP_OFFSET 0x8000
247 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
251 * The hardware state:
253 struct x86_hw_tss x86_tss;
256 * The extra 1 is there because the CPU will access an
257 * additional byte beyond the end of the IO permission
258 * bitmap. The extra byte must be all 1 bits, and must
259 * be within the limit.
261 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
263 * Cache the current maximum and the last task that used the bitmap:
265 unsigned long io_bitmap_max;
266 struct thread_struct *io_bitmap_owner;
269 * Pad the TSS to be cacheline-aligned (size is 0x100):
271 unsigned long __cacheline_filler[35];
273 * .. and then another 0x100 bytes for the emergency kernel stack:
275 unsigned long stack[64];
277 } __attribute__((packed));
279 DECLARE_PER_CPU(struct tss_struct, init_tss);
282 * Save the original ist values for checking stack pointers during debugging
285 unsigned long ist[7];
288 #define MXCSR_DEFAULT 0x1f80
290 struct i387_fsave_struct {
291 u32 cwd; /* FPU Control Word */
292 u32 swd; /* FPU Status Word */
293 u32 twd; /* FPU Tag Word */
294 u32 fip; /* FPU IP Offset */
295 u32 fcs; /* FPU IP Selector */
296 u32 foo; /* FPU Operand Pointer Offset */
297 u32 fos; /* FPU Operand Pointer Selector */
299 /* 8*10 bytes for each FP-reg = 80 bytes: */
302 /* Software status information [not touched by FSAVE ]: */
306 struct i387_fxsave_struct {
307 u16 cwd; /* Control Word */
308 u16 swd; /* Status Word */
309 u16 twd; /* Tag Word */
310 u16 fop; /* Last Instruction Opcode */
313 u64 rip; /* Instruction Pointer */
314 u64 rdp; /* Data Pointer */
317 u32 fip; /* FPU IP Offset */
318 u32 fcs; /* FPU IP Selector */
319 u32 foo; /* FPU Operand Offset */
320 u32 fos; /* FPU Operand Selector */
323 u32 mxcsr; /* MXCSR Register State */
324 u32 mxcsr_mask; /* MXCSR Mask */
326 /* 8*16 bytes for each FP-reg = 128 bytes: */
329 /* 16*16 bytes for each XMM-reg = 256 bytes: */
334 } __attribute__((aligned(16)));
336 struct i387_soft_struct {
344 /* 8*10 bytes for each FP-reg = 80 bytes: */
356 union thread_xstate {
357 struct i387_fsave_struct fsave;
358 struct i387_fxsave_struct fxsave;
359 struct i387_soft_struct soft;
363 DECLARE_PER_CPU(struct orig_ist, orig_ist);
366 extern void print_cpu_info(struct cpuinfo_x86 *);
367 extern unsigned int xstate_size;
368 extern void free_thread_xstate(struct task_struct *);
369 extern struct kmem_cache *task_xstate_cachep;
370 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
371 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
372 extern unsigned short num_cache_leaves;
374 struct thread_struct {
375 /* Cached TLS descriptors: */
376 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
380 unsigned long sysenter_cs;
382 unsigned long usersp; /* Copy from PDA */
385 unsigned short fsindex;
386 unsigned short gsindex;
391 /* Hardware debugging registers: */
392 unsigned long debugreg0;
393 unsigned long debugreg1;
394 unsigned long debugreg2;
395 unsigned long debugreg3;
396 unsigned long debugreg6;
397 unsigned long debugreg7;
400 unsigned long trap_no;
401 unsigned long error_code;
402 /* floating point and extended processor state */
403 union thread_xstate *xstate;
405 /* Virtual 86 mode info */
406 struct vm86_struct __user *vm86_info;
407 unsigned long screen_bitmap;
408 unsigned long v86flags;
409 unsigned long v86mask;
410 unsigned long saved_sp0;
411 unsigned int saved_fs;
412 unsigned int saved_gs;
414 /* IO permissions: */
415 unsigned long *io_bitmap_ptr;
417 /* Max allowed port in the bitmap, in bytes: */
418 unsigned io_bitmap_max;
419 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
420 unsigned long debugctlmsr;
421 /* Debug Store - if not 0 points to a DS Save Area configuration;
422 * goes into MSR_IA32_DS_AREA */
423 unsigned long ds_area_msr;
426 static inline unsigned long native_get_debugreg(int regno)
428 unsigned long val = 0; /* Damn you, gcc! */
432 asm("mov %%db0, %0" :"=r" (val));
435 asm("mov %%db1, %0" :"=r" (val));
438 asm("mov %%db2, %0" :"=r" (val));
441 asm("mov %%db3, %0" :"=r" (val));
444 asm("mov %%db6, %0" :"=r" (val));
447 asm("mov %%db7, %0" :"=r" (val));
455 static inline void native_set_debugreg(int regno, unsigned long value)
459 asm("mov %0, %%db0" ::"r" (value));
462 asm("mov %0, %%db1" ::"r" (value));
465 asm("mov %0, %%db2" ::"r" (value));
468 asm("mov %0, %%db3" ::"r" (value));
471 asm("mov %0, %%db6" ::"r" (value));
474 asm("mov %0, %%db7" ::"r" (value));
482 * Set IOPL bits in EFLAGS from given mask
484 static inline void native_set_iopl_mask(unsigned mask)
489 asm volatile ("pushfl;"
496 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
501 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
503 tss->x86_tss.sp0 = thread->sp0;
505 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
506 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
507 tss->x86_tss.ss1 = thread->sysenter_cs;
508 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
513 static inline void native_swapgs(void)
516 asm volatile("swapgs" ::: "memory");
520 #ifdef CONFIG_PARAVIRT
521 #include <asm/paravirt.h>
523 #define __cpuid native_cpuid
524 #define paravirt_enabled() 0
527 * These special macros can be used to get or set a debugging register
529 #define get_debugreg(var, register) \
530 (var) = native_get_debugreg(register)
531 #define set_debugreg(value, register) \
532 native_set_debugreg(register, value)
534 static inline void load_sp0(struct tss_struct *tss,
535 struct thread_struct *thread)
537 native_load_sp0(tss, thread);
540 #define set_iopl_mask native_set_iopl_mask
541 #define SWAPGS swapgs
542 #endif /* CONFIG_PARAVIRT */
545 * Save the cr4 feature set we're using (ie
546 * Pentium 4MB enable and PPro Global page
547 * enable), so that any CPU's that boot up
548 * after us can get the correct flags.
550 extern unsigned long mmu_cr4_features;
552 static inline void set_in_cr4(unsigned long mask)
556 mmu_cr4_features |= mask;
562 static inline void clear_in_cr4(unsigned long mask)
566 mmu_cr4_features &= ~mask;
572 struct microcode_header {
580 unsigned int datasize;
581 unsigned int totalsize;
582 unsigned int reserved[3];
586 struct microcode_header hdr;
587 unsigned int bits[0];
590 typedef struct microcode microcode_t;
591 typedef struct microcode_header microcode_header_t;
593 /* microcode format is extended from prescott processors */
594 struct extended_signature {
600 struct extended_sigtable {
603 unsigned int reserved[3];
604 struct extended_signature sigs[0];
613 * create a kernel thread without removing it from tasklists
615 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
617 /* Free all resources held by a thread. */
618 extern void release_thread(struct task_struct *);
620 /* Prepare to copy thread state - unlazy all lazy state */
621 extern void prepare_to_copy(struct task_struct *tsk);
623 unsigned long get_wchan(struct task_struct *p);
626 * Generic CPUID function
627 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
628 * resulting in stale register contents being returned.
630 static inline void cpuid(unsigned int op,
631 unsigned int *eax, unsigned int *ebx,
632 unsigned int *ecx, unsigned int *edx)
636 __cpuid(eax, ebx, ecx, edx);
639 /* Some CPUID calls want 'count' to be placed in ecx */
640 static inline void cpuid_count(unsigned int op, int count,
641 unsigned int *eax, unsigned int *ebx,
642 unsigned int *ecx, unsigned int *edx)
646 __cpuid(eax, ebx, ecx, edx);
650 * CPUID functions returning a single datum
652 static inline unsigned int cpuid_eax(unsigned int op)
654 unsigned int eax, ebx, ecx, edx;
656 cpuid(op, &eax, &ebx, &ecx, &edx);
661 static inline unsigned int cpuid_ebx(unsigned int op)
663 unsigned int eax, ebx, ecx, edx;
665 cpuid(op, &eax, &ebx, &ecx, &edx);
670 static inline unsigned int cpuid_ecx(unsigned int op)
672 unsigned int eax, ebx, ecx, edx;
674 cpuid(op, &eax, &ebx, &ecx, &edx);
679 static inline unsigned int cpuid_edx(unsigned int op)
681 unsigned int eax, ebx, ecx, edx;
683 cpuid(op, &eax, &ebx, &ecx, &edx);
688 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
689 static inline void rep_nop(void)
691 asm volatile("rep; nop" ::: "memory");
694 static inline void cpu_relax(void)
699 /* Stop speculative execution: */
700 static inline void sync_core(void)
704 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
705 : "ebx", "ecx", "edx", "memory");
708 static inline void __monitor(const void *eax, unsigned long ecx,
711 /* "monitor %eax, %ecx, %edx;" */
712 asm volatile(".byte 0x0f, 0x01, 0xc8;"
713 :: "a" (eax), "c" (ecx), "d"(edx));
716 static inline void __mwait(unsigned long eax, unsigned long ecx)
718 /* "mwait %eax, %ecx;" */
719 asm volatile(".byte 0x0f, 0x01, 0xc9;"
720 :: "a" (eax), "c" (ecx));
723 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
726 /* "mwait %eax, %ecx;" */
727 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
728 :: "a" (eax), "c" (ecx));
731 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
733 extern int force_mwait;
735 extern void select_idle_routine(const struct cpuinfo_x86 *c);
737 extern unsigned long boot_option_idle_override;
739 extern void enable_sep_cpu(void);
740 extern int sysenter_setup(void);
742 /* Defined in head.S */
743 extern struct desc_ptr early_gdt_descr;
745 extern void cpu_set_gdt(int);
746 extern void switch_to_new_gdt(void);
747 extern void cpu_init(void);
748 extern void init_gdt(int cpu);
750 static inline void update_debugctlmsr(unsigned long debugctlmsr)
752 #ifndef CONFIG_X86_DEBUGCTLMSR
753 if (boot_cpu_data.x86 < 6)
756 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
760 * from system description table in BIOS. Mostly for MCA use, but
761 * others may find it useful:
763 extern unsigned int machine_id;
764 extern unsigned int machine_submodel_id;
765 extern unsigned int BIOS_revision;
767 /* Boot loader type from the setup header: */
768 extern int bootloader_type;
770 extern char ignore_fpu_irq;
772 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
773 #define ARCH_HAS_PREFETCHW
774 #define ARCH_HAS_SPINLOCK_PREFETCH
777 # define BASE_PREFETCH ASM_NOP4
778 # define ARCH_HAS_PREFETCH
780 # define BASE_PREFETCH "prefetcht0 (%1)"
784 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
786 * It's not worth to care about 3dnow prefetches for the K6
787 * because they are microcoded there and very slow.
789 static inline void prefetch(const void *x)
791 alternative_input(BASE_PREFETCH,
798 * 3dnow prefetch to get an exclusive cache line.
799 * Useful for spinlocks to avoid one state transition in the
800 * cache coherency protocol:
802 static inline void prefetchw(const void *x)
804 alternative_input(BASE_PREFETCH,
810 static inline void spin_lock_prefetch(const void *x)
817 * User space process size: 3GB (default).
819 #define TASK_SIZE PAGE_OFFSET
820 #define STACK_TOP TASK_SIZE
821 #define STACK_TOP_MAX STACK_TOP
823 #define INIT_THREAD { \
824 .sp0 = sizeof(init_stack) + (long)&init_stack, \
826 .sysenter_cs = __KERNEL_CS, \
827 .io_bitmap_ptr = NULL, \
828 .fs = __KERNEL_PERCPU, \
832 * Note that the .io_bitmap member must be extra-big. This is because
833 * the CPU will access an additional byte beyond the end of the IO
834 * permission bitmap. The extra byte must be all 1 bits, and must
835 * be within the limit.
839 .sp0 = sizeof(init_stack) + (long)&init_stack, \
840 .ss0 = __KERNEL_DS, \
841 .ss1 = __KERNEL_CS, \
842 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
844 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
847 extern unsigned long thread_saved_pc(struct task_struct *tsk);
849 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
850 #define KSTK_TOP(info) \
852 unsigned long *__ptr = (unsigned long *)(info); \
853 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
857 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
858 * This is necessary to guarantee that the entire "struct pt_regs"
859 * is accessable even if the CPU haven't stored the SS/ESP registers
860 * on the stack (interrupt gate does not save these registers
861 * when switching to the same priv ring).
862 * Therefore beware: accessing the ss/esp fields of the
863 * "struct pt_regs" is possible, but they may contain the
864 * completely wrong values.
866 #define task_pt_regs(task) \
868 struct pt_regs *__regs__; \
869 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
873 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
877 * User space process size. 47bits minus one guard page.
879 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
881 /* This decides where the kernel will search for a free chunk of vm
882 * space during mmap's.
884 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
885 0xc0000000 : 0xFFFFe000)
887 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
888 IA32_PAGE_OFFSET : TASK_SIZE64)
889 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
890 IA32_PAGE_OFFSET : TASK_SIZE64)
892 #define STACK_TOP TASK_SIZE
893 #define STACK_TOP_MAX TASK_SIZE64
895 #define INIT_THREAD { \
896 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
900 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
904 * Return saved PC of a blocked thread.
905 * What is this good for? it will be always the scheduler or ret_from_fork.
907 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
909 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
910 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
911 #endif /* CONFIG_X86_64 */
913 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
914 unsigned long new_sp);
917 * This decides where the kernel will search for a free chunk of vm
918 * space during mmap's.
920 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
922 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
924 /* Get/set a process' ability to use the timestamp counter instruction */
925 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
926 #define SET_TSC_CTL(val) set_tsc_mode((val))
928 extern int get_tsc_mode(unsigned long adr);
929 extern int set_tsc_mode(unsigned int val);