2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
13 #include <linux/sched.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/regset.h>
16 #include <linux/hardirq.h>
18 #include <asm/processor.h>
19 #include <asm/sigcontext.h>
21 #include <asm/uaccess.h>
23 extern void fpu_init(void);
24 extern void mxcsr_feature_mask_init(void);
25 extern int init_fpu(struct task_struct *child);
26 extern asmlinkage void math_state_restore(void);
27 extern void init_thread_xstate(void);
29 extern user_regset_active_fn fpregs_active, xfpregs_active;
30 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
31 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
33 #ifdef CONFIG_IA32_EMULATION
35 extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
36 extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
41 /* Ignore delayed exceptions from user space */
42 static inline void tolerant_fwait(void)
44 asm volatile("1: fwait\n"
46 _ASM_EXTABLE(1b, 2b));
49 static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
53 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
55 ".section .fixup,\"ax\"\n"
56 "3: movl $-1,%[err]\n"
61 #if 0 /* See comment in __save_init_fpu() below. */
62 : [fx] "r" (fx), "m" (*fx), "0" (0));
64 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
71 #define X87_FSW_ES (1 << 7) /* Exception Summary */
73 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
74 is pending. Clear the x87 state here by setting it to fixed
75 values. The kernel data segment can be sometimes 0 and sometimes
76 new user value. Both should be ok.
77 Use the PDA as safe address because it should be already in L1. */
78 static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
80 if (unlikely(fx->swd & X87_FSW_ES))
81 asm volatile("fnclex");
82 alternative_input(ASM_NOP8 ASM_NOP2,
83 " emms\n" /* clear stack tags */
84 " fildl %%gs:0", /* load to clear state */
85 X86_FEATURE_FXSAVE_LEAK);
88 static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
92 asm volatile("1: rex64/fxsave (%[fx])\n\t"
94 ".section .fixup,\"ax\"\n"
95 "3: movl $-1,%[err]\n"
99 : [err] "=r" (err), "=m" (*fx)
100 #if 0 /* See comment in __fxsave_clear() below. */
101 : [fx] "r" (fx), "0" (0));
103 : [fx] "cdaSDb" (fx), "0" (0));
106 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
108 /* No need to clear here because the caller clears USED_MATH */
112 static inline void __save_init_fpu(struct task_struct *tsk)
114 /* Using "rex64; fxsave %0" is broken because, if the memory operand
115 uses any extended registers for addressing, a second REX prefix
116 will be generated (to the assembler, rex64 followed by semicolon
117 is a separate instruction), and hence the 64-bitness is lost. */
119 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
120 starting with gas 2.16. */
121 __asm__ __volatile__("fxsaveq %0"
122 : "=m" (tsk->thread.xstate->fxsave));
124 /* Using, as a workaround, the properly prefixed form below isn't
125 accepted by any binutils version so far released, complaining that
126 the same type of prefix is used twice if an extended register is
127 needed for addressing (fix submitted to mainline 2005-11-21). */
128 __asm__ __volatile__("rex64/fxsave %0"
129 : "=m" (tsk->thread.xstate->fxsave));
131 /* This, however, we can work around by forcing the compiler to select
132 an addressing mode that doesn't require extended registers. */
133 __asm__ __volatile__("rex64/fxsave (%1)"
134 : "=m" (tsk->thread.xstate->fxsave)
135 : "cdaSDb" (&tsk->thread.xstate->fxsave));
137 clear_fpu_state(&tsk->thread.xstate->fxsave);
138 task_thread_info(tsk)->status &= ~TS_USEDFPU;
141 #else /* CONFIG_X86_32 */
143 extern void finit(void);
145 static inline void tolerant_fwait(void)
147 asm volatile("fnclex ; fwait");
150 static inline void restore_fpu(struct task_struct *tsk)
153 * The "nop" is needed to make the instructions the same
160 "m" (tsk->thread.xstate->fxsave));
163 /* We need a safe address that is cheap to find and that is already
164 in L1 during context switch. The best choices are unfortunately
165 different for UP and SMP */
167 #define safe_address (__per_cpu_offset[0])
169 #define safe_address (kstat_cpu(0).cpustat.user)
173 * These must be called with preempt disabled
175 static inline void __save_init_fpu(struct task_struct *tsk)
177 /* Use more nops than strictly needed in case the compiler
180 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
182 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
184 [fx] "m" (tsk->thread.xstate->fxsave),
185 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
186 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
187 is pending. Clear the x87 state here by setting it to fixed
188 values. safe_address is a random variable that should be in L1 */
190 GENERIC_NOP8 GENERIC_NOP2,
191 "emms\n\t" /* clear stack tags */
192 "fildl %[addr]", /* set F?P to defined value */
193 X86_FEATURE_FXSAVE_LEAK,
194 [addr] "m" (safe_address));
195 task_thread_info(tsk)->status &= ~TS_USEDFPU;
199 * Signal frame handlers...
201 extern int save_i387(struct _fpstate __user *buf);
202 extern int restore_i387(struct _fpstate __user *buf);
204 #endif /* CONFIG_X86_64 */
206 static inline void __unlazy_fpu(struct task_struct *tsk)
208 if (task_thread_info(tsk)->status & TS_USEDFPU) {
209 __save_init_fpu(tsk);
212 tsk->fpu_counter = 0;
215 static inline void __clear_fpu(struct task_struct *tsk)
217 if (task_thread_info(tsk)->status & TS_USEDFPU) {
219 task_thread_info(tsk)->status &= ~TS_USEDFPU;
224 static inline void kernel_fpu_begin(void)
226 struct thread_info *me = current_thread_info();
228 if (me->status & TS_USEDFPU)
229 __save_init_fpu(me->task);
234 static inline void kernel_fpu_end(void)
241 * Some instructions like VIA's padlock instructions generate a spurious
242 * DNA fault but don't modify SSE registers. And these instructions
243 * get used from interrupt context aswell. To prevent these kernel instructions
244 * in interrupt context interact wrongly with other user/kernel fpu usage, we
245 * should use them only in the context of irq_ts_save/restore()
247 static inline int irq_ts_save(void)
250 * If we are in process context, we are ok to take a spurious DNA fault.
251 * Otherwise, doing clts() in process context require pre-emption to
252 * be disabled or some heavy lifting like kernel_fpu_begin()
257 if (read_cr0() & X86_CR0_TS) {
265 static inline void irq_ts_restore(int TS_state)
273 static inline void save_init_fpu(struct task_struct *tsk)
275 __save_init_fpu(tsk);
279 #define unlazy_fpu __unlazy_fpu
280 #define clear_fpu __clear_fpu
282 #else /* CONFIG_X86_32 */
285 * These disable preemption on their own and are safe
287 static inline void save_init_fpu(struct task_struct *tsk)
290 __save_init_fpu(tsk);
295 static inline void unlazy_fpu(struct task_struct *tsk)
302 static inline void clear_fpu(struct task_struct *tsk)
309 #endif /* CONFIG_X86_64 */
312 * i387 state interaction
314 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
317 return tsk->thread.xstate->fxsave.cwd;
319 return (unsigned short)tsk->thread.xstate->fsave.cwd;
323 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
326 return tsk->thread.xstate->fxsave.swd;
328 return (unsigned short)tsk->thread.xstate->fsave.swd;
332 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
335 return tsk->thread.xstate->fxsave.mxcsr;
337 return MXCSR_DEFAULT;
341 #endif /* _ASM_X86_I387_H */