4 #include <linux/config.h>
7 #include <asm/hypervisor.h>
10 * For the 8k pagesize kernel, use only 10 hw context bits to optimize some
11 * shifts in the fast tlbmiss handlers, instead of all 13 bits (specifically
12 * for vpte offset calculation). For other pagesizes, this optimization in
13 * the tlbhandlers can not be done; but still, all 13 bits can not be used
14 * because the tlb handlers use "andcc" instruction which sign extends 13
18 #define CTX_NR_BITS 10
20 #define CTX_NR_BITS 12
23 #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
25 /* UltraSPARC-III+ and later have a feature whereby you can
26 * select what page size the various Data-TLB instances in the
27 * chip. In order to gracefully support this, we put the version
28 * field in a spot outside of the areas of the context register
29 * where this parameter is specified.
31 #define CTX_VERSION_SHIFT 22
32 #define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
34 #define CTX_PGSZ_8KB _AC(0x0,UL)
35 #define CTX_PGSZ_64KB _AC(0x1,UL)
36 #define CTX_PGSZ_512KB _AC(0x2,UL)
37 #define CTX_PGSZ_4MB _AC(0x3,UL)
38 #define CTX_PGSZ_BITS _AC(0x7,UL)
39 #define CTX_PGSZ0_NUC_SHIFT 61
40 #define CTX_PGSZ1_NUC_SHIFT 58
41 #define CTX_PGSZ0_SHIFT 16
42 #define CTX_PGSZ1_SHIFT 19
43 #define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
44 (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
46 #if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
47 #define CTX_PGSZ_BASE CTX_PGSZ_8KB
48 #elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
49 #define CTX_PGSZ_BASE CTX_PGSZ_64KB
50 #elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)
51 #define CTX_PGSZ_BASE CTX_PGSZ_512KB
52 #elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)
53 #define CTX_PGSZ_BASE CTX_PGSZ_4MB
55 #error No page size specified in kernel configuration
58 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
59 #define CTX_PGSZ_HUGE CTX_PGSZ_4MB
60 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
61 #define CTX_PGSZ_HUGE CTX_PGSZ_512KB
62 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
63 #define CTX_PGSZ_HUGE CTX_PGSZ_64KB
66 #define CTX_PGSZ_KERN CTX_PGSZ_4MB
68 /* Thus, when running on UltraSPARC-III+ and later, we use the following
69 * PRIMARY_CONTEXT register values for the kernel context.
71 #define CTX_CHEETAH_PLUS_NUC \
72 ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
73 (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
75 #define CTX_CHEETAH_PLUS_CTX0 \
76 ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
77 (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
79 /* If you want "the TLB context number" use CTX_NR_MASK. If you
80 * want "the bits I program into the context registers" use
83 #define CTX_NR_MASK TAG_CONTEXT_BITS
84 #define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK)
86 #define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
87 #define CTX_VALID(__ctx) \
88 (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
89 #define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
90 #define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
94 #define TSB_ENTRY_ALIGNMENT 16
99 } __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
101 extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
102 extern void tsb_flush(unsigned long ent, unsigned long tag);
105 unsigned long sparc64_ctx_val;
107 unsigned long tsb_rss_limit;
108 unsigned long tsb_nentries;
109 unsigned long tsb_reg_val;
110 unsigned long tsb_map_vaddr;
111 unsigned long tsb_map_pte;
112 struct hv_tsb_descr tsb_descr;
115 #endif /* !__ASSEMBLY__ */