1 /* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
2 * irq.h: IRQ registers on the 64-bit Sparc.
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
11 #include <linux/linkage.h>
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/interrupt.h>
16 #include <asm/ptrace.h>
20 #define MAX_IRQ_DESC_ACTION 4
23 void (*pre_handler)(struct ino_bucket *, void *, void *);
24 void *pre_handler_arg1;
25 void *pre_handler_arg2;
26 u32 action_active_mask;
27 struct irqaction action[MAX_IRQ_DESC_ACTION];
30 /* You should not mess with this directly. That's the job of irq.c.
32 * If you make changes here, please update hand coded assembler of
33 * the vectored interrupt trap handler in entry.S -DaveM
35 * This is currently one DCACHE line, two buckets per L2 cache
36 * line. Keep this in mind please.
39 /* Next handler in per-CPU PIL worklist. We know that
40 * bucket pointers have the high 32-bits clear, so to
41 * save space we only store the bits we need.
43 /*0x00*/unsigned int irq_chain;
45 /* PIL to schedule this IVEC at. */
46 /*0x04*/unsigned char pil;
48 /* If an IVEC arrives while irq_info is NULL, we
49 * set this to notify request_irq() about the event.
51 /*0x05*/unsigned char pending;
53 /* Miscellaneous flags. */
54 /*0x06*/unsigned char flags;
56 /* Currently unused. */
57 /*0x07*/unsigned char __pad;
59 /* Reference to IRQ descriptor for this bucket. */
60 /*0x08*/struct irq_desc *irq_info;
62 /* Sun5 Interrupt Clear Register. */
63 /*0x10*/unsigned long iclr;
65 /* Sun5 Interrupt Mapping Register. */
66 /*0x18*/unsigned long imap;
70 /* IMAP/ICLR register defines */
71 #define IMAP_VALID 0x80000000 /* IRQ Enabled */
72 #define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
73 #define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
74 #define IMAP_TID_SHIFT 26
75 #define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
76 #define IMAP_AID_SHIFT 26
77 #define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
78 #define IMAP_NID_SHIFT 21
79 #define IMAP_IGN 0x000007c0 /* IRQ Group Number */
80 #define IMAP_INO 0x0000003f /* IRQ Number */
81 #define IMAP_INR 0x000007ff /* Full interrupt number*/
83 #define ICLR_IDLE 0x00000000 /* Idle state */
84 #define ICLR_TRANSMIT 0x00000001 /* Transmit state */
85 #define ICLR_PENDING 0x00000003 /* Pending state */
87 /* Only 8-bits are available, be careful. -DaveM */
88 #define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */
89 #define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/
90 #define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
92 #define NUM_IVECS (IMAP_INR + 1)
93 extern struct ino_bucket ivector_table[NUM_IVECS];
95 #define __irq_ino(irq) \
96 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
97 #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
98 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
99 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
101 static __inline__ char *__irq_itoa(unsigned int irq)
103 static char buff[16];
105 sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
111 #define irq_canonicalize(irq) (irq)
112 extern void disable_irq(unsigned int);
113 #define disable_irq_nosync disable_irq
114 extern void enable_irq(unsigned int);
115 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
116 extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags);
117 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
119 static __inline__ void set_softint(unsigned long bits)
121 __asm__ __volatile__("wr %0, 0x0, %%set_softint"
126 static __inline__ void clear_softint(unsigned long bits)
128 __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
133 static __inline__ unsigned long get_softint(void)
135 unsigned long retval;
137 __asm__ __volatile__("rd %%softint, %0"
144 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);