1 /* cpudata.h: Per-cpu parameters.
3 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
6 #ifndef _SPARC64_CPUDATA_H
7 #define _SPARC64_CPUDATA_H
9 #include <asm/hypervisor.h>
13 #include <linux/percpu.h>
14 #include <linux/threads.h>
18 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
19 unsigned int multiplier;
21 unsigned int idle_volume;
22 unsigned long clock_tick; /* %tick's per second */
23 unsigned long udelay_val;
25 /* Dcache line 2, rarely used */
26 unsigned int dcache_size;
27 unsigned int dcache_line_size;
28 unsigned int icache_size;
29 unsigned int icache_line_size;
30 unsigned int ecache_size;
31 unsigned int ecache_line_size;
36 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
37 #define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
38 #define local_cpu_data() __get_cpu_var(__cpu_data)
40 /* Trap handling code needs to get at a few critical values upon
41 * trap entry and to process TSB misses. These cannot be in the
42 * per_cpu() area as we really need to lock them into the TLB and
43 * thus make them part of the main kernel image. As a result we
44 * try to make this as small as possible.
46 * This is padded out and aligned to 64-bytes to avoid false sharing
50 /* If you modify the size of this structure, please update
51 * TRAP_BLOCK_SZ_SHIFT below.
56 struct thread_info *thread;
57 unsigned long pgd_paddr;
58 unsigned long __pad1[2];
61 unsigned long __pad2[4];
63 /* Dcache lines 3 and 4 */
64 struct hv_fault_status fault_info;
65 } __attribute__((aligned(64)));
66 extern struct trap_per_cpu trap_block[NR_CPUS];
67 extern void init_cur_cpu_trap(void);
68 extern void setup_tba(void);
71 struct cpuid_patch_entry {
73 unsigned int cheetah_safari[4];
74 unsigned int cheetah_jbus[4];
75 unsigned int starfire[4];
76 unsigned int sun4v[4];
78 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
81 struct gl_1insn_patch_entry {
85 extern struct gl_1insn_patch_entry __gl_1insn_patch, __gl_1insn_patch_end;
87 struct gl_2insn_patch_entry {
89 unsigned int insns[2];
91 extern struct gl_2insn_patch_entry __gl_2insn_patch, __gl_2insn_patch_end;
92 #endif /* !(__ASSEMBLY__) */
94 #define TRAP_PER_CPU_THREAD 0x00
95 #define TRAP_PER_CPU_PGD_PADDR 0x08
96 #define TRAP_PER_CPU_FAULT_INFO 0x20
98 #define TRAP_BLOCK_SZ_SHIFT 7
100 #include <asm/scratchpad.h>
104 #define __GET_CPUID(REG) \
105 /* Spitfire implementation (default). */ \
106 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
108 and REG, 0x1f, REG; \
110 .section .cpuid_patch, "ax"; \
111 /* Instruction location. */ \
113 /* Cheetah Safari implementation. */ \
114 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
116 and REG, 0x3ff, REG; \
118 /* Cheetah JBUS implementation. */ \
119 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
121 and REG, 0x1f, REG; \
123 /* Starfire implementation. */ \
124 sethi %hi(0x1fff40000d0 >> 9), REG; \
127 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
128 /* sun4v implementation. */ \
129 mov SCRATCHPAD_CPUID, REG; \
131 ldxa [REG] ASI_SCRATCHPAD, REG; \
135 /* Clobbers TMP, current address space PGD phys address into DEST. */
136 #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
138 sethi %hi(trap_block), DEST; \
139 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
140 or DEST, %lo(trap_block), DEST; \
141 add DEST, TMP, DEST; \
142 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
144 /* Clobbers TMP, loads local processor's IRQ work area into DEST. */
145 #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
147 sethi %hi(__irq_work), DEST; \
149 or DEST, %lo(__irq_work), DEST; \
152 /* Clobbers TMP, loads DEST with current thread info pointer. */
153 #define TRAP_LOAD_THREAD_REG(DEST, TMP) \
155 sethi %hi(trap_block), DEST; \
156 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
157 or DEST, %lo(trap_block), DEST; \
158 ldx [DEST + TMP], DEST;
160 /* Given the current thread info pointer in THR, load the per-cpu
161 * area base of the current processor into DEST. REG1, REG2, and REG3 are
164 * You absolutely cannot use DEST as a temporary in this code. The
165 * reason is that traps can happen during execution, and return from
166 * trap will load the fully resolved DEST per-cpu base. This can corrupt
167 * the calculations done by the macro mid-stream.
169 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
170 ldub [THR + TI_CPU], REG1; \
171 sethi %hi(__per_cpu_shift), REG3; \
172 sethi %hi(__per_cpu_base), REG2; \
173 ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
174 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
175 sllx REG1, REG3, REG3; \
176 add REG3, REG2, DEST;
180 /* Uniprocessor versions, we know the cpuid is zero. */
181 #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
182 sethi %hi(trap_block), DEST; \
183 or DEST, %lo(trap_block), DEST; \
184 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
186 #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
187 sethi %hi(__irq_work), DEST; \
188 or DEST, %lo(__irq_work), DEST;
190 #define TRAP_LOAD_THREAD_REG(DEST, TMP) \
191 sethi %hi(trap_block), DEST; \
192 ldx [DEST + %lo(trap_block)], DEST;
194 /* No per-cpu areas on uniprocessor, so no need to load DEST. */
195 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
197 #endif /* !(CONFIG_SMP) */
199 #endif /* _SPARC64_CPUDATA_H */