1 /* cpudata.h: Per-cpu parameters.
3 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
6 #ifndef _SPARC64_CPUDATA_H
7 #define _SPARC64_CPUDATA_H
11 #include <linux/percpu.h>
12 #include <linux/threads.h>
16 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
17 unsigned int multiplier;
19 unsigned int idle_volume;
20 unsigned long clock_tick; /* %tick's per second */
21 unsigned long udelay_val;
23 /* Dcache line 2, rarely used */
24 unsigned int dcache_size;
25 unsigned int dcache_line_size;
26 unsigned int icache_size;
27 unsigned int icache_line_size;
28 unsigned int ecache_size;
29 unsigned int ecache_line_size;
34 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
35 #define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
36 #define local_cpu_data() __get_cpu_var(__cpu_data)
38 /* Trap handling code needs to get at a few critical values upon
39 * trap entry and to process TSB misses. These cannot be in the
40 * per_cpu() area as we really need to lock them into the TLB and
41 * thus make them part of the main kernel image. As a result we
42 * try to make this as small as possible.
44 * This is padded out and aligned to 64-bytes to avoid false sharing
48 /* If you modify the size of this structure, please update
49 * TRAP_BLOCK_SZ_SHIFT below.
54 struct thread_info *thread;
55 unsigned long pgd_paddr;
56 unsigned long __pad1[2];
59 unsigned long __pad2[4];
60 } __attribute__((aligned(64)));
61 extern struct trap_per_cpu trap_block[NR_CPUS];
62 extern void init_cur_cpu_trap(void);
63 extern void setup_tba(void);
66 struct cpuid_patch_entry {
68 unsigned int cheetah_safari[4];
69 unsigned int cheetah_jbus[4];
70 unsigned int starfire[4];
71 unsigned int sun4v[4];
73 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
76 struct gl_1insn_patch_entry {
80 extern struct gl_1insn_patch_entry __gl_1insn_patch, __gl_1insn_patch_end;
81 #endif /* !(__ASSEMBLY__) */
83 #define TRAP_PER_CPU_THREAD 0x00
84 #define TRAP_PER_CPU_PGD_PADDR 0x08
86 #define TRAP_BLOCK_SZ_SHIFT 6
88 #include <asm/scratchpad.h>
92 #define __GET_CPUID(REG) \
93 /* Spitfire implementation (default). */ \
94 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
98 .section .cpuid_patch, "ax"; \
99 /* Instruction location. */ \
101 /* Cheetah Safari implementation. */ \
102 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
104 and REG, 0x3ff, REG; \
106 /* Cheetah JBUS implementation. */ \
107 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
109 and REG, 0x1f, REG; \
111 /* Starfire implementation. */ \
112 sethi %hi(0x1fff40000d0 >> 9), REG; \
115 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
116 /* sun4v implementation. */ \
117 mov SCRATCHPAD_CPUID, REG; \
119 ldxa [REG] ASI_SCRATCHPAD, REG; \
123 /* Clobbers TMP, current address space PGD phys address into DEST. */
124 #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
126 sethi %hi(trap_block), DEST; \
127 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
128 or DEST, %lo(trap_block), DEST; \
129 add DEST, TMP, DEST; \
130 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
132 /* Clobbers TMP, loads local processor's IRQ work area into DEST. */
133 #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
135 sethi %hi(__irq_work), DEST; \
137 or DEST, %lo(__irq_work), DEST; \
140 /* Clobbers TMP, loads DEST with current thread info pointer. */
141 #define TRAP_LOAD_THREAD_REG(DEST, TMP) \
143 sethi %hi(trap_block), DEST; \
144 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
145 or DEST, %lo(trap_block), DEST; \
146 ldx [DEST + TMP], DEST;
148 /* Given the current thread info pointer in THR, load the per-cpu
149 * area base of the current processor into DEST. REG1, REG2, and REG3 are
152 * You absolutely cannot use DEST as a temporary in this code. The
153 * reason is that traps can happen during execution, and return from
154 * trap will load the fully resolved DEST per-cpu base. This can corrupt
155 * the calculations done by the macro mid-stream.
157 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
158 ldub [THR + TI_CPU], REG1; \
159 sethi %hi(__per_cpu_shift), REG3; \
160 sethi %hi(__per_cpu_base), REG2; \
161 ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
162 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
163 sllx REG1, REG3, REG3; \
164 add REG3, REG2, DEST;
168 /* Uniprocessor versions, we know the cpuid is zero. */
169 #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
170 sethi %hi(trap_block), DEST; \
171 or DEST, %lo(trap_block), DEST; \
172 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
174 #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
175 sethi %hi(__irq_work), DEST; \
176 or DEST, %lo(__irq_work), DEST;
178 #define TRAP_LOAD_THREAD_REG(DEST, TMP) \
179 sethi %hi(trap_block), DEST; \
180 ldx [DEST + %lo(trap_block)], DEST;
182 /* No per-cpu areas on uniprocessor, so no need to load DEST. */
183 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
185 #endif /* !(CONFIG_SMP) */
187 #endif /* _SPARC64_CPUDATA_H */