1 /* cpudata.h: Per-cpu parameters.
3 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
6 #ifndef _SPARC64_CPUDATA_H
7 #define _SPARC64_CPUDATA_H
11 #include <linux/percpu.h>
12 #include <linux/threads.h>
16 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
17 unsigned int multiplier;
19 unsigned int idle_volume;
20 unsigned long clock_tick; /* %tick's per second */
21 unsigned long udelay_val;
23 /* Dcache line 2, rarely used */
24 unsigned int dcache_size;
25 unsigned int dcache_line_size;
26 unsigned int icache_size;
27 unsigned int icache_line_size;
28 unsigned int ecache_size;
29 unsigned int ecache_line_size;
34 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
35 #define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
36 #define local_cpu_data() __get_cpu_var(__cpu_data)
38 /* Trap handling code needs to get at a few critical values upon
39 * trap entry and to process TSB misses. These cannot be in the
40 * per_cpu() area as we really need to lock them into the TLB and
41 * thus make them part of the main kernel image. As a result we
42 * try to make this as small as possible.
44 * This is padded out and aligned to 64-bytes to avoid false sharing
48 /* If you modify the size of this structure, please update
49 * TRAP_BLOCK_SZ_SHIFT below.
54 struct thread_info *thread;
55 unsigned long pgd_paddr;
56 unsigned long __pad1[2];
59 unsigned long __pad2[4];
60 } __attribute__((aligned(64)));
61 extern struct trap_per_cpu trap_block[NR_CPUS];
62 extern void init_cur_cpu_trap(void);
63 extern void per_cpu_patch(void);
64 extern void setup_tba(void);
66 #endif /* !(__ASSEMBLY__) */
68 #define TRAP_PER_CPU_THREAD 0x00
69 #define TRAP_PER_CPU_PGD_PADDR 0x08
71 #define TRAP_BLOCK_SZ_SHIFT 6
73 /* Clobbers %g1, loads %g6 with local processor's cpuid */
75 ba,pt %xcc, __get_cpu_id; \
78 /* Clobbers %g1, current address space PGD phys address into %g7. */
79 #define TRAP_LOAD_PGD_PHYS \
81 sllx %g6, TRAP_BLOCK_SZ_SHIFT, %g6; \
82 sethi %hi(trap_block), %g7; \
83 or %g7, %lo(trap_block), %g7; \
85 ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7;
87 /* Clobbers %g1, loads local processor's IRQ work area into %g6. */
88 #define TRAP_LOAD_IRQ_WORK \
90 sethi %hi(__irq_work), %g1; \
92 or %g1, %lo(__irq_work), %g1; \
95 /* Clobbers %g1, loads %g6 with current thread info pointer. */
96 #define TRAP_LOAD_THREAD_REG \
98 sllx %g6, TRAP_BLOCK_SZ_SHIFT, %g6; \
99 sethi %hi(trap_block), %g1; \
100 or %g1, %lo(trap_block), %g1; \
101 ldx [%g1 + %g6], %g6;
103 /* Given the current thread info pointer in %g6, load the per-cpu
104 * area base of the current processor into %g5. REG1, REG2, and REG3 are
107 * You absolutely cannot use %g5 as a temporary in this code. The
108 * reason is that traps can happen during execution, and return from
109 * trap will load the fully resolved %g5 per-cpu base. This can corrupt
110 * the calculations done by the macro mid-stream.
113 #define LOAD_PER_CPU_BASE(REG1, REG2, REG3) \
114 ldub [%g6 + TI_CPU], REG1; \
115 sethi %hi(__per_cpu_shift), REG3; \
116 sethi %hi(__per_cpu_base), REG2; \
117 ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
118 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
119 sllx REG1, REG3, REG3; \
122 #define LOAD_PER_CPU_BASE(REG1, REG2, REG3)
125 #endif /* _SPARC64_CPUDATA_H */