1 /* cpudata.h: Per-cpu parameters.
3 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
6 #ifndef _SPARC64_CPUDATA_H
7 #define _SPARC64_CPUDATA_H
11 #include <linux/percpu.h>
12 #include <linux/threads.h>
16 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
17 unsigned int multiplier;
19 unsigned int idle_volume;
20 unsigned long clock_tick; /* %tick's per second */
21 unsigned long udelay_val;
23 /* Dcache line 2, rarely used */
24 unsigned int dcache_size;
25 unsigned int dcache_line_size;
26 unsigned int icache_size;
27 unsigned int icache_line_size;
28 unsigned int ecache_size;
29 unsigned int ecache_line_size;
34 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
35 #define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
36 #define local_cpu_data() __get_cpu_var(__cpu_data)
38 /* Trap handling code needs to get at a few critical values upon
39 * trap entry and to process TSB misses. These cannot be in the
40 * per_cpu() area as we really need to lock them into the TLB and
41 * thus make them part of the main kernel image. As a result we
42 * try to make this as small as possible.
44 * This is padded out and aligned to 64-bytes to avoid false sharing
48 /* If you modify the size of this structure, please update
49 * TRAP_BLOCK_SZ_SHIFT below.
54 struct thread_info *thread;
55 unsigned long pgd_paddr;
56 unsigned long __pad1[2];
59 unsigned long __pad2[4];
60 } __attribute__((aligned(64)));
61 extern struct trap_per_cpu trap_block[NR_CPUS];
62 extern void init_cur_cpu_trap(void);
63 extern void setup_tba(void);
66 struct cpuid_patch_entry {
68 unsigned int cheetah_safari[4];
69 unsigned int cheetah_jbus[4];
70 unsigned int starfire[4];
72 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
75 #endif /* !(__ASSEMBLY__) */
77 #define TRAP_PER_CPU_THREAD 0x00
78 #define TRAP_PER_CPU_PGD_PADDR 0x08
80 #define TRAP_BLOCK_SZ_SHIFT 6
84 #define __GET_CPUID(REG) \
85 /* Spitfire implementation (default). */ \
86 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
90 .section .cpuid_patch, "ax"; \
91 /* Instruction location. */ \
93 /* Cheetah Safari implementation. */ \
94 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
96 and REG, 0x3ff, REG; \
98 /* Cheetah JBUS implementation. */ \
99 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
101 and REG, 0x1f, REG; \
103 /* Starfire implementation. */ \
104 sethi %hi(0x1fff40000d0 >> 9), REG; \
107 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
110 /* Clobbers %g1, current address space PGD phys address into %g7. */
111 #define TRAP_LOAD_PGD_PHYS \
113 sethi %hi(trap_block), %g7; \
114 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1; \
115 or %g7, %lo(trap_block), %g7; \
117 ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7;
119 /* Clobbers %g1, loads local processor's IRQ work area into %g6. */
120 #define TRAP_LOAD_IRQ_WORK \
122 sethi %hi(__irq_work), %g6; \
124 or %g6, %lo(__irq_work), %g6; \
127 /* Clobbers %g1, loads %g6 with current thread info pointer. */
128 #define TRAP_LOAD_THREAD_REG \
130 sethi %hi(trap_block), %g6; \
131 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1; \
132 or %g6, %lo(trap_block), %g6; \
133 ldx [%g6 + %g1], %g6;
135 /* Given the current thread info pointer in %g6, load the per-cpu
136 * area base of the current processor into %g5. REG1, REG2, and REG3 are
139 * You absolutely cannot use %g5 as a temporary in this code. The
140 * reason is that traps can happen during execution, and return from
141 * trap will load the fully resolved %g5 per-cpu base. This can corrupt
142 * the calculations done by the macro mid-stream.
144 #define LOAD_PER_CPU_BASE(REG1, REG2, REG3) \
145 ldub [%g6 + TI_CPU], REG1; \
146 sethi %hi(__per_cpu_shift), REG3; \
147 sethi %hi(__per_cpu_base), REG2; \
148 ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
149 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
150 sllx REG1, REG3, REG3; \
155 /* Uniprocessor versions, we know the cpuid is zero. */
156 #define TRAP_LOAD_PGD_PHYS \
157 sethi %hi(trap_block), %g7; \
158 or %g7, %lo(trap_block), %g7; \
159 ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7;
161 #define TRAP_LOAD_IRQ_WORK \
162 sethi %hi(__irq_work), %g6; \
163 or %g6, %lo(__irq_work), %g6;
165 #define TRAP_LOAD_THREAD_REG \
166 sethi %hi(trap_block), %g6; \
167 ldx [%g6 + %lo(trap_block)], %g6;
169 /* No per-cpu areas on uniprocessor, so no need to load %g5. */
170 #define LOAD_PER_CPU_BASE(REG1, REG2, REG3)
172 #endif /* !(CONFIG_SMP) */
174 #endif /* _SPARC64_CPUDATA_H */