err.no Git - linux-2.6/blob - include/asm-sparc/system.h

   1 #ifndef __SPARC_SYSTEM_H
   2 #define __SPARC_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <linux/threads.h>      /* NR_CPUS */
   6 #include <linux/thread_info.h>
   7
   8 #include <asm/page.h>
   9 #include <asm/psr.h>
  10 #include <asm/ptrace.h>
  11 #include <asm/btfixup.h>
  12 #include <asm/smp.h>
  13
  14 #ifndef __ASSEMBLY__
  15
  16 #include <linux/irqflags.h>
  17
  18 /*
  19  * Sparc (general) CPU types
  20  */
  21 enum sparc_cpu {
  22   sun4        = 0x00,
  23   sun4c       = 0x01,
  24   sun4m       = 0x02,
  25   sun4d       = 0x03,
  26   sun4e       = 0x04,
  27   sun4u       = 0x05, /* V8 ploos ploos */
  28   sun_unknown = 0x06,
  29   ap1000      = 0x07, /* almost a sun4m */
  30 };
  31
  32 /* Really, userland should not be looking at any of this... */
  33 #ifdef __KERNEL__
  34
  35 extern enum sparc_cpu sparc_cpu_model;
  36
  37 #ifndef CONFIG_SUN4
  38 #define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
  39 #define ARCH_SUN4 0
  40 #else
  41 #define ARCH_SUN4C_SUN4 1
  42 #define ARCH_SUN4 1
  43 #endif
  44
  45 #define SUN4M_NCPUS            4              /* Architectural limit of sun4m. */
  46
  47 extern struct thread_info *current_set[NR_CPUS];
  48
  49 extern unsigned long empty_bad_page;
  50 extern unsigned long empty_bad_page_table;
  51 extern unsigned long empty_zero_page;
  52
  53 extern void sun_do_break(void);
  54 extern int serial_console;
  55 extern int stop_a_enabled;
  56
  57 static inline int con_is_present(void)
  58 {
  59         return serial_console ? 0 : 1;
  60 }
  61
  62 /* When a context switch happens we must flush all user windows so that
  63  * the windows of the current process are flushed onto its stack. This
  64  * way the windows are all clean for the next process and the stack
  65  * frames are up to date.
  66  */
  67 extern void flush_user_windows(void);
  68 extern void kill_user_windows(void);
  69 extern void synchronize_user_stack(void);
  70 extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
  71                    void *fpqueue, unsigned long *fpqdepth);
  72
  73 #ifdef CONFIG_SMP
  74 #define SWITCH_ENTER(prv) \
  75         do {                    \
  76         if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
  77                 put_psr(get_psr() | PSR_EF); \
  78                 fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
  79                        &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
  80                 clear_tsk_thread_flag(prv, TIF_USEDFPU); \
  81                 (prv)->thread.kregs->psr &= ~PSR_EF; \
  82         } \
  83         } while(0)
  84
  85 #define SWITCH_DO_LAZY_FPU(next)        /* */
  86 #else
  87 #define SWITCH_ENTER(prv)               /* */
  88 #define SWITCH_DO_LAZY_FPU(nxt) \
  89         do {                    \
  90         if (last_task_used_math != (nxt))               \
  91                 (nxt)->thread.kregs->psr&=~PSR_EF;      \
  92         } while(0)
  93 #endif
  94
  95 /*
  96  * Flush windows so that the VM switch which follows
  97  * would not pull the stack from under us.
  98  *
  99  * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
 100  * XXX WTF is the above comment? Found in late teen 2.4.x.
 101  */
 102 #define prepare_arch_switch(next) do { \
 103         __asm__ __volatile__( \
 104         ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
 105         "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
 106         "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
 107         "save %sp, -0x40, %sp\n\t" \
 108         "restore; restore; restore; restore; restore; restore; restore"); \
 109 } while(0)
 110
 111         /* Much care has gone into this code, do not touch it.
 112          *
 113          * We need to loadup regs l0/l1 for the newly forked child
 114          * case because the trap return path relies on those registers
 115          * holding certain values, gcc is told that they are clobbered.
 116          * Gcc needs registers for 3 values in and 1 value out, so we
 117          * clobber every non-fixed-usage register besides l2/l3/o4/o5.  -DaveM
 118          *
 119          * Hey Dave, that do not touch sign is too much of an incentive
 120          * - Anton & Pete
 121          */
 122 #define switch_to(prev, next, last) do {                                                \
 123         SWITCH_ENTER(prev);                                                             \
 124         SWITCH_DO_LAZY_FPU(next);                                                       \
 125         cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask);                      \
 126         __asm__ __volatile__(                                                           \
 127         "sethi  %%hi(here - 0x8), %%o7\n\t"                                             \
 128         "mov    %%g6, %%g3\n\t"                                                         \
 129         "or     %%o7, %%lo(here - 0x8), %%o7\n\t"                                       \
 130         "rd     %%psr, %%g4\n\t"                                                        \
 131         "std    %%sp, [%%g6 + %4]\n\t"                                                  \
 132         "rd     %%wim, %%g5\n\t"                                                        \
 133         "wr     %%g4, 0x20, %%psr\n\t"                                                  \
 134         "nop\n\t"                                                                       \
 135         "std    %%g4, [%%g6 + %3]\n\t"                                                  \
 136         "ldd    [%2 + %3], %%g4\n\t"                                                    \
 137         "mov    %2, %%g6\n\t"                                                           \
 138         ".globl patchme_store_new_current\n"                                            \
 139 "patchme_store_new_current:\n\t"                                                        \
 140         "st     %2, [%1]\n\t"                                                           \
 141         "wr     %%g4, 0x20, %%psr\n\t"                                                  \
 142         "nop\n\t"                                                                       \
 143         "nop\n\t"                                                                       \
 144         "nop\n\t"       /* LEON needs all 3 nops: load to %sp depends on CWP. */                \
 145         "ldd    [%%g6 + %4], %%sp\n\t"                                                  \
 146         "wr     %%g5, 0x0, %%wim\n\t"                                                   \
 147         "ldd    [%%sp + 0x00], %%l0\n\t"                                                \
 148         "ldd    [%%sp + 0x38], %%i6\n\t"                                                \
 149         "wr     %%g4, 0x0, %%psr\n\t"                                                   \
 150         "nop\n\t"                                                                       \
 151         "nop\n\t"                                                                       \
 152         "jmpl   %%o7 + 0x8, %%g0\n\t"                                                   \
 153         " ld    [%%g3 + %5], %0\n\t"                                                    \
 154         "here:\n"                                                                       \
 155         : "=&r" (last)                                                                  \
 156         : "r" (&(current_set[hard_smp_processor_id()])),        \
 157           "r" (task_thread_info(next)),                         \
 158           "i" (TI_KPSR),                                        \
 159           "i" (TI_KSP),                                         \
 160           "i" (TI_TASK)                                         \
 161         :       "g1", "g2", "g3", "g4", "g5",       "g7",       \
 162           "l0", "l1",       "l3", "l4", "l5", "l6", "l7",       \
 163           "i0", "i1", "i2", "i3", "i4", "i5",                   \
 164           "o0", "o1", "o2", "o3",                   "o7");      \
 165         } while(0)
 166
 167 /* XXX Change this if we ever use a PSO mode kernel. */
 168 #define mb()    __asm__ __volatile__ ("" : : : "memory")
 169 #define rmb()   mb()
 170 #define wmb()   mb()
 171 #define read_barrier_depends()  do { } while(0)
 172 #define set_mb(__var, __value)  do { __var = __value; mb(); } while(0)
 173 #define smp_mb()        __asm__ __volatile__("":::"memory")
 174 #define smp_rmb()       __asm__ __volatile__("":::"memory")
 175 #define smp_wmb()       __asm__ __volatile__("":::"memory")
 176 #define smp_read_barrier_depends()      do { } while(0)
 177
 178 #define nop() __asm__ __volatile__ ("nop")
 179
 180 /* This has special calling conventions */
 181 #ifndef CONFIG_SMP
 182 BTFIXUPDEF_CALL(void, ___xchg32, void)
 183 #endif
 184
 185 static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
 186 {
 187 #ifdef CONFIG_SMP
 188         __asm__ __volatile__("swap [%2], %0"
 189                              : "=&r" (val)
 190                              : "0" (val), "r" (m)
 191                              : "memory");
 192         return val;
 193 #else
 194         register unsigned long *ptr asm("g1");
 195         register unsigned long ret asm("g2");
 196
 197         ptr = (unsigned long *) m;
 198         ret = val;
 199
 200         /* Note: this is magic and the nop there is
 201            really needed. */
 202         __asm__ __volatile__(
 203         "mov    %%o7, %%g4\n\t"
 204         "call   ___f____xchg32\n\t"
 205         " nop\n\t"
 206         : "=&r" (ret)
 207         : "0" (ret), "r" (ptr)
 208         : "g3", "g4", "g7", "memory", "cc");
 209
 210         return ret;
 211 #endif
 212 }
 213
 214 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 215
 216 extern void __xchg_called_with_bad_pointer(void);
 217
 218 static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
 219 {
 220         switch (size) {
 221         case 4:
 222                 return xchg_u32(ptr, x);
 223         };
 224         __xchg_called_with_bad_pointer();
 225         return x;
 226 }
 227
 228 /* Emulate cmpxchg() the same way we emulate atomics,
 229  * by hashing the object address and indexing into an array
 230  * of spinlocks to get a bit of performance...
 231  *
 232  * See arch/sparc/lib/atomic32.c for implementation.
 233  *
 234  * Cribbed from <asm-parisc/atomic.h>
 235  */
 236 #define __HAVE_ARCH_CMPXCHG     1
 237
 238 /* bug catcher for when unsupported size is used - won't link */
 239 extern void __cmpxchg_called_with_bad_pointer(void);
 240 /* we only need to support cmpxchg of a u32 on sparc */
 241 extern unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_);
 242
 243 /* don't worry...optimizer will get rid of most of this */
 244 static inline unsigned long
 245 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
 246 {
 247         switch (size) {
 248         case 4:
 249                 return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_);
 250         default:
 251                 __cmpxchg_called_with_bad_pointer();
 252                 break;
 253         }
 254         return old;
 255 }
 256
 257 #define cmpxchg(ptr, o, n)                                              \
 258 ({                                                                      \
 259         __typeof__(*(ptr)) _o_ = (o);                                   \
 260         __typeof__(*(ptr)) _n_ = (n);                                   \
 261         (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,       \
 262                         (unsigned long)_n_, sizeof(*(ptr)));            \
 263 })
 264
 265 #include <asm-generic/cmpxchg-local.h>
 266
 267 /*
 268  * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 269  * them available.
 270  */
 271 #define cmpxchg_local(ptr, o, n)                                               \
 272         ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
 273                         (unsigned long)(n), sizeof(*(ptr))))
 274 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 275
 276 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
 277
 278 #endif /* __KERNEL__ */
 279
 280 #endif /* __ASSEMBLY__ */
 281
 282 #define arch_align_stack(x) (x)
 283
 284 #endif /* !(__SPARC_SYSTEM_H) */