1 #ifndef __ASM_SH_SYSTEM_H
2 #define __ASM_SH_SYSTEM_H
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
9 #include <linux/irqflags.h>
10 #include <linux/compiler.h>
11 #include <linux/linkage.h>
12 #include <asm/types.h>
13 #include <asm/ptrace.h>
15 #define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */
17 #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
20 unsigned long __addr; \
21 __addr = 0xa8000000; \
22 __asm__ __volatile__( \
25 : "m" (__m(__addr))); \
30 * A brief note on ctrl_barrier(), the control register write barrier.
32 * Legacy SH cores typically require a sequence of 8 nops after
33 * modification of a control register in order for the changes to take
34 * effect. On newer cores (like the sh4a and sh5) this is accomplished
37 * Also note that on sh4a in the icbi case we can forego a synco for the
38 * write barrier, as it's not necessary for control registers.
40 * Historically we have only done this type of barrier for the MMUCR, but
41 * it's also necessary for the CCR, so we make it generic here instead.
43 #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
44 #define mb() __asm__ __volatile__ ("synco": : :"memory")
46 #define wmb() __asm__ __volatile__ ("synco": : :"memory")
47 #define ctrl_barrier() __icbi()
48 #define read_barrier_depends() do { } while(0)
50 #define mb() __asm__ __volatile__ ("": : :"memory")
52 #define wmb() __asm__ __volatile__ ("": : :"memory")
53 #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
54 #define read_barrier_depends() do { } while(0)
59 #define smp_rmb() rmb()
60 #define smp_wmb() wmb()
61 #define smp_read_barrier_depends() read_barrier_depends()
63 #define smp_mb() barrier()
64 #define smp_rmb() barrier()
65 #define smp_wmb() barrier()
66 #define smp_read_barrier_depends() do { } while(0)
69 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
71 static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
73 unsigned long flags, retval;
75 local_irq_save(flags);
78 local_irq_restore(flags);
82 static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
84 unsigned long flags, retval;
86 local_irq_save(flags);
89 local_irq_restore(flags);
93 extern void __xchg_called_with_bad_pointer(void);
95 #define __xchg(ptr, x, size) \
97 unsigned long __xchg__res; \
98 volatile void *__xchg_ptr = (ptr); \
101 __xchg__res = xchg_u32(__xchg_ptr, x); \
104 __xchg__res = xchg_u8(__xchg_ptr, x); \
107 __xchg_called_with_bad_pointer(); \
115 #define xchg(ptr,x) \
116 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
118 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
124 local_irq_save(flags);
128 local_irq_restore(flags); /* implies memory barrier */
132 /* This function doesn't exist, so you'll get a linker error
133 * if something tries to do an invalid cmpxchg(). */
134 extern void __cmpxchg_called_with_bad_pointer(void);
136 #define __HAVE_ARCH_CMPXCHG 1
138 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
139 unsigned long new, int size)
143 return __cmpxchg_u32(ptr, old, new);
145 __cmpxchg_called_with_bad_pointer();
149 #define cmpxchg(ptr,o,n) \
151 __typeof__(*(ptr)) _o_ = (o); \
152 __typeof__(*(ptr)) _n_ = (n); \
153 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
154 (unsigned long)_n_, sizeof(*(ptr))); \
157 extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
159 extern void *set_exception_table_vec(unsigned int vec, void *handler);
161 static inline void *set_exception_table_evt(unsigned int evt, void *handler)
163 return set_exception_table_vec(evt >> 5, handler);
167 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
169 #ifdef CONFIG_CPU_SH2A
170 extern unsigned int instruction_size(unsigned int insn);
171 #elif defined(CONFIG_SUPERH32)
172 #define instruction_size(insn) (2)
174 #define instruction_size(insn) (4)
178 * disable hlt during certain critical i/o operations
180 #define HAVE_DISABLE_HLT
181 void disable_hlt(void);
182 void enable_hlt(void);
184 void default_idle(void);
185 void per_cpu_trap_init(void);
187 asmlinkage void break_point_trap(void);
188 asmlinkage void debug_trap_handler(unsigned long r4, unsigned long r5,
189 unsigned long r6, unsigned long r7,
190 struct pt_regs __regs);
191 asmlinkage void bug_trap_handler(unsigned long r4, unsigned long r5,
192 unsigned long r6, unsigned long r7,
193 struct pt_regs __regs);
195 #define arch_align_stack(x) (x)
197 #ifdef CONFIG_SUPERH32
198 # include "system_32.h"
200 # include "system_64.h"