2 * This file contains the functions and defines necessary to modify and
3 * use the SuperH page table tree.
5 * Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2002 - 2007 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
12 #ifndef __ASM_SH_PGTABLE_H
13 #define __ASM_SH_PGTABLE_H
15 #include <asm-generic/pgtable-nopmd.h>
19 #include <asm/addrspace.h>
20 #include <asm/fixmap.h>
23 * ZERO_PAGE is a global shared page that is always zero: used
24 * for zero-mapped memory areas etc..
26 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
27 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
29 #endif /* !__ASSEMBLY__ */
32 * Effective and physical address definitions, to aid with sign
36 #define NEFF_SIGN (1LL << (NEFF - 1))
37 #define NEFF_MASK (-1LL << NEFF)
45 #define NPHYS_SIGN (1LL << (NPHYS - 1))
46 #define NPHYS_MASK (-1LL << NPHYS)
49 * traditional two-level paging structure
52 #if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
53 # define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
55 # define PTE_MAGNITUDE 2 /* 32-bit PTEs */
57 #define PTE_SHIFT PAGE_SHIFT
58 #define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
61 #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
62 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
63 #define PGDIR_MASK (~(PGDIR_SIZE-1))
65 /* Entries per level */
66 #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
67 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
69 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
70 #define FIRST_USER_ADDRESS 0
72 #define PTE_PHYS_MASK (0x20000000 - PAGE_SIZE)
74 #ifdef CONFIG_SUPERH32
75 #define VMALLOC_START (P3SEG)
77 #define VMALLOC_START (0xf0000000)
79 #define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
81 #if defined(CONFIG_SUPERH32)
82 #include <asm/pgtable_32.h>
84 #include <asm/pgtable_64.h>
88 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
89 * protection for execute, and considers it the same as a read. Also, write
90 * permission implies read permission. This is the closest we can get..
92 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
93 * not only supporting separate execute, read, and write bits, but having
94 * completely separate permission bits for user and kernel space.
97 #define __P000 PAGE_NONE
98 #define __P001 PAGE_READONLY
99 #define __P010 PAGE_COPY
100 #define __P011 PAGE_COPY
101 #define __P100 PAGE_EXECREAD
102 #define __P101 PAGE_EXECREAD
103 #define __P110 PAGE_COPY
104 #define __P111 PAGE_COPY
106 #define __S000 PAGE_NONE
107 #define __S001 PAGE_READONLY
108 #define __S010 PAGE_WRITEONLY
109 #define __S011 PAGE_SHARED
110 #define __S100 PAGE_EXECREAD
111 #define __S101 PAGE_EXECREAD
112 #define __S110 PAGE_RWX
113 #define __S111 PAGE_RWX
115 typedef pte_t *pte_addr_t;
117 #define kern_addr_valid(addr) (1)
119 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
120 remap_pfn_range(vma, vaddr, pfn, size, prot)
122 #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
125 * No page table caches to initialise
127 #define pgtable_cache_init() do { } while (0)
129 #if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
130 defined(CONFIG_SH7705_CACHE_32KB))
132 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
133 pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
136 struct vm_area_struct;
137 extern void update_mmu_cache(struct vm_area_struct * vma,
138 unsigned long address, pte_t pte);
139 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
140 extern void paging_init(void);
142 #include <asm-generic/pgtable.h>
144 #endif /* __ASM_SH_PGTABLE_H */