2 * include/asm-sh/cpu-sh4/mmu_context.h
4 * Copyright (C) 1999 Niibe Yutaka
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
11 #define __ASM_CPU_SH4_MMU_CONTEXT_H
13 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
14 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15 #define MMU_TTB 0xFF000008 /* Translation table base register */
16 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
17 #define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
19 #define MMUCR 0xFF000010 /* MMU Control Register */
21 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22 #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23 #define MMU_PAGE_ASSOC_BIT 0x80
26 #define MMUCR_ME (1 << 7)
31 #ifdef CONFIG_SH_STORE_QUEUES
32 #define MMUCR_SQMD (1 << 9)
34 #define MMUCR_SQMD (0)
37 #define MMU_NTLB_ENTRIES 64
38 #define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME)
40 #define MMU_ITLB_DATA_ARRAY 0xF3000000
41 #define MMU_UTLB_DATA_ARRAY 0xF7000000
43 #define MMU_UTLB_ENTRIES 64
44 #define MMU_U_ENTRY_SHIFT 8
45 #define MMU_UTLB_VALID 0x100
46 #define MMU_ITLB_ENTRIES 4
47 #define MMU_I_ENTRY_SHIFT 8
48 #define MMU_ITLB_VALID 0x100
50 #define TRA 0xff000020
51 #define EXPEVT 0xff000024
52 #define INTEVT 0xff000028
54 #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */