2 * include/asm-s390/system.h
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
8 * Derived from "include/asm-i386/system.h"
11 #ifndef __ASM_SYSTEM_H
12 #define __ASM_SYSTEM_H
14 #include <linux/kernel.h>
15 #include <asm/types.h>
16 #include <asm/ptrace.h>
17 #include <asm/setup.h>
18 #include <asm/processor.h>
24 extern struct task_struct *__switch_to(void *, void *);
27 #define __FLAG_SHIFT 56
28 #else /* ! __s390x__ */
29 #define __FLAG_SHIFT 24
30 #endif /* ! __s390x__ */
32 static inline void save_fp_regs(s390_fp_regs *fpregs)
39 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
40 if (!MACHINE_HAS_IEEE)
56 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
59 static inline void restore_fp_regs(s390_fp_regs *fpregs)
66 : : "a" (fpregs), "m" (*fpregs) );
67 if (!MACHINE_HAS_IEEE)
83 : : "a" (fpregs), "m" (*fpregs) );
86 static inline void save_access_regs(unsigned int *acrs)
88 asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
91 static inline void restore_access_regs(unsigned int *acrs)
93 asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
96 #define switch_to(prev,next,last) do { \
99 save_fp_regs(&prev->thread.fp_regs); \
100 restore_fp_regs(&next->thread.fp_regs); \
101 save_access_regs(&prev->thread.acrs[0]); \
102 restore_access_regs(&next->thread.acrs[0]); \
103 prev = __switch_to(prev,next); \
107 * On SMP systems, when the scheduler does migration-cost autodetection,
108 * it needs a way to flush as much of the CPU's caches as possible.
110 * TODO: fill this in!
112 static inline void sched_cacheflush(void)
116 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
117 extern void account_vtime(struct task_struct *);
118 extern void account_tick_vtime(struct task_struct *);
119 extern void account_system_vtime(struct task_struct *);
121 #define account_vtime(x) do { /* empty */ } while (0)
124 #define finish_arch_switch(prev) do { \
125 set_fs(current->thread.mm_segment); \
126 account_vtime(prev); \
129 #define nop() __asm__ __volatile__ ("nop")
131 #define xchg(ptr,x) \
132 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))
134 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
136 unsigned long addr, old;
141 addr = (unsigned long) ptr;
142 shift = (3 ^ (addr & 3)) << 3;
151 : "=&d" (old), "=m" (*(int *) addr)
152 : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
153 "m" (*(int *) addr) : "memory", "cc", "0" );
157 addr = (unsigned long) ptr;
158 shift = (2 ^ (addr & 2)) << 3;
167 : "=&d" (old), "=m" (*(int *) addr)
168 : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
169 "m" (*(int *) addr) : "memory", "cc", "0" );
175 "0: cs %0,%2,0(%3)\n"
177 : "=&d" (old), "=m" (*(int *) ptr)
178 : "d" (x), "a" (ptr), "m" (*(int *) ptr)
186 "0: csg %0,%2,0(%3)\n"
188 : "=&d" (old), "=m" (*(long *) ptr)
189 : "d" (x), "a" (ptr), "m" (*(long *) ptr)
193 #endif /* __s390x__ */
199 * Atomic compare and exchange. Compare OLD with MEM, if identical,
200 * store NEW in MEM. Return the initial value in MEM. Success is
201 * indicated by comparing RETURN with OLD.
204 #define __HAVE_ARCH_CMPXCHG 1
206 #define cmpxchg(ptr,o,n)\
207 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
208 (unsigned long)(n),sizeof(*(ptr))))
210 static inline unsigned long
211 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
213 unsigned long addr, prev, tmp;
218 addr = (unsigned long) ptr;
219 shift = (3 ^ (addr & 3)) << 3;
233 : "=&d" (prev), "=&d" (tmp)
234 : "d" (old << shift), "d" (new << shift), "a" (ptr),
235 "d" (~(255 << shift))
237 return prev >> shift;
239 addr = (unsigned long) ptr;
240 shift = (2 ^ (addr & 2)) << 3;
254 : "=&d" (prev), "=&d" (tmp)
255 : "d" (old << shift), "d" (new << shift), "a" (ptr),
256 "d" (~(65535 << shift))
258 return prev >> shift;
262 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
269 : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
272 #endif /* __s390x__ */
278 * Force strict CPU ordering.
279 * And yes, this is required on UP too when we're talking
282 * This is very similar to the ppc eieio/sync instruction in that is
283 * does a checkpoint syncronisation & makes sure that
284 * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
287 #define eieio() __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
288 # define SYNC_OTHER_CORES(x) eieio()
290 #define rmb() eieio()
291 #define wmb() eieio()
292 #define read_barrier_depends() do { } while(0)
293 #define smp_mb() mb()
294 #define smp_rmb() rmb()
295 #define smp_wmb() wmb()
296 #define smp_read_barrier_depends() read_barrier_depends()
297 #define smp_mb__before_clear_bit() smp_mb()
298 #define smp_mb__after_clear_bit() smp_mb()
301 #define set_mb(var, value) do { var = value; mb(); } while (0)
305 #define __ctl_load(array, low, high) ({ \
306 typedef struct { char _[sizeof(array)]; } addrtype; \
307 __asm__ __volatile__ ( \
309 " lctlg 0,0,0(%0)\n" \
311 : : "a" (&array), "a" (((low)<<4)+(high)), \
312 "m" (*(addrtype *)(array)) : "1" ); \
315 #define __ctl_store(array, low, high) ({ \
316 typedef struct { char _[sizeof(array)]; } addrtype; \
317 __asm__ __volatile__ ( \
319 " stctg 0,0,0(%1)\n" \
321 : "=m" (*(addrtype *)(array)) \
322 : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
325 #define __ctl_set_bit(cr, bit) ({ \
327 __asm__ __volatile__ ( \
328 " bras 1,0f\n" /* skip indirect insns */ \
329 " stctg 0,0,0(%1)\n" \
330 " lctlg 0,0,0(%1)\n" \
331 "0: ex %2,0(1)\n" /* execute stctl */ \
333 " ogr 0,%3\n" /* set the bit */ \
335 "1: ex %2,6(1)" /* execute lctl */ \
337 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
338 "a" (cr*17), "a" (1L<<(bit)) \
339 : "cc", "0", "1" ); \
342 #define __ctl_clear_bit(cr, bit) ({ \
344 __asm__ __volatile__ ( \
345 " bras 1,0f\n" /* skip indirect insns */ \
346 " stctg 0,0,0(%1)\n" \
347 " lctlg 0,0,0(%1)\n" \
348 "0: ex %2,0(1)\n" /* execute stctl */ \
350 " ngr 0,%3\n" /* set the bit */ \
352 "1: ex %2,6(1)" /* execute lctl */ \
354 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
355 "a" (cr*17), "a" (~(1L<<(bit))) \
356 : "cc", "0", "1" ); \
359 #else /* __s390x__ */
361 #define __ctl_load(array, low, high) ({ \
362 typedef struct { char _[sizeof(array)]; } addrtype; \
363 __asm__ __volatile__ ( \
365 " lctl 0,0,0(%0)\n" \
367 : : "a" (&array), "a" (((low)<<4)+(high)), \
368 "m" (*(addrtype *)(array)) : "1" ); \
371 #define __ctl_store(array, low, high) ({ \
372 typedef struct { char _[sizeof(array)]; } addrtype; \
373 __asm__ __volatile__ ( \
375 " stctl 0,0,0(%1)\n" \
377 : "=m" (*(addrtype *)(array)) \
378 : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
381 #define __ctl_set_bit(cr, bit) ({ \
383 __asm__ __volatile__ ( \
384 " bras 1,0f\n" /* skip indirect insns */ \
385 " stctl 0,0,0(%1)\n" \
386 " lctl 0,0,0(%1)\n" \
387 "0: ex %2,0(1)\n" /* execute stctl */ \
389 " or 0,%3\n" /* set the bit */ \
391 "1: ex %2,4(1)" /* execute lctl */ \
393 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
394 "a" (cr*17), "a" (1<<(bit)) \
395 : "cc", "0", "1" ); \
398 #define __ctl_clear_bit(cr, bit) ({ \
400 __asm__ __volatile__ ( \
401 " bras 1,0f\n" /* skip indirect insns */ \
402 " stctl 0,0,0(%1)\n" \
403 " lctl 0,0,0(%1)\n" \
404 "0: ex %2,0(1)\n" /* execute stctl */ \
406 " nr 0,%3\n" /* set the bit */ \
408 "1: ex %2,4(1)" /* execute lctl */ \
410 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
411 "a" (cr*17), "a" (~(1<<(bit))) \
412 : "cc", "0", "1" ); \
414 #endif /* __s390x__ */
416 #include <linux/irqflags.h>
419 * Use to set psw mask except for the first byte which
420 * won't be changed by this function.
423 __set_psw_mask(unsigned long mask)
425 local_save_flags(mask);
426 __load_psw_mask(mask);
429 #define local_mcck_enable() __set_psw_mask(PSW_KERNEL_BITS)
430 #define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
434 extern void smp_ctl_set_bit(int cr, int bit);
435 extern void smp_ctl_clear_bit(int cr, int bit);
436 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
437 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
441 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
442 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
444 #endif /* CONFIG_SMP */
446 extern void (*_machine_restart)(char *command);
447 extern void (*_machine_halt)(void);
448 extern void (*_machine_power_off)(void);
450 #define arch_align_stack(x) (x)
452 #endif /* __KERNEL__ */