1 #ifndef _PPC64_PGTABLE_H
2 #define _PPC64_PGTABLE_H
5 * This file contains the functions and defines necessary to modify and use
6 * the ppc64 hashed page table.
10 #include <linux/config.h>
11 #include <linux/stddef.h>
12 #include <asm/processor.h> /* For TASK_SIZE */
15 #include <asm/tlbflush.h>
16 #endif /* __ASSEMBLY__ */
18 #include <asm-generic/pgtable-nopud.h>
20 /* PMD_SHIFT determines what a second-level page table entry can map */
21 #define PMD_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
22 #define PMD_SIZE (1UL << PMD_SHIFT)
23 #define PMD_MASK (~(PMD_SIZE-1))
25 /* PGDIR_SHIFT determines what a third-level page table entry can map */
26 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3) + (PAGE_SHIFT - 2))
27 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
28 #define PGDIR_MASK (~(PGDIR_SIZE-1))
31 * Entries per page directory level. The PTE level must use a 64b record
32 * for each page table entry. The PMD and PGD level use a 32b record for
33 * each entry by assuming that each entry is page aligned.
35 #define PTE_INDEX_SIZE 9
36 #define PMD_INDEX_SIZE 10
37 #define PGD_INDEX_SIZE 10
39 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
40 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
41 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
43 #define USER_PTRS_PER_PGD (1024)
44 #define FIRST_USER_ADDRESS 0
46 #define EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
47 PGD_INDEX_SIZE + PAGE_SHIFT)
50 * Size of EA range mapped by our pagetables.
52 #define PGTABLE_EA_BITS 41
53 #define PGTABLE_EA_MASK ((1UL<<PGTABLE_EA_BITS)-1)
56 * Define the address range of the vmalloc VM area.
58 #define VMALLOC_START (0xD000000000000000ul)
59 #define VMALLOC_END (VMALLOC_START + PGTABLE_EA_MASK)
62 * Define the address range of the imalloc VM area.
65 #define IMALLOC_START (ioremap_bot)
66 #define IMALLOC_VMADDR(x) ((unsigned long)(x))
67 #define PHBS_IO_BASE (0xE000000000000000ul) /* Reserve 2 gigs for PHBs */
68 #define IMALLOC_BASE (0xE000000080000000ul)
69 #define IMALLOC_END (IMALLOC_BASE + PGTABLE_EA_MASK)
72 * Define the user address range
74 #define USER_START (0UL)
75 #define USER_END (USER_START + PGTABLE_EA_MASK)
79 * Bits in a linux-style PTE. These match the bits in the
80 * (hardware-defined) PowerPC PTE as closely as possible.
82 #define _PAGE_PRESENT 0x0001 /* software: pte contains a translation */
83 #define _PAGE_USER 0x0002 /* matches one of the PP bits */
84 #define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
85 #define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
86 #define _PAGE_GUARDED 0x0008
87 #define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */
88 #define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
89 #define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
90 #define _PAGE_DIRTY 0x0080 /* C: page changed */
91 #define _PAGE_ACCESSED 0x0100 /* R: page referenced */
92 #define _PAGE_RW 0x0200 /* software: user write access allowed */
93 #define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
94 #define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
95 #define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
96 #define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
97 #define _PAGE_HUGE 0x10000 /* 16MB page */
98 /* Bits 0x7000 identify the index within an HPT Group */
99 #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_SECONDARY | _PAGE_GROUP_IX)
100 /* PAGE_MASK gives the right answer below, but only by accident */
101 /* It should be preserving the high 48 bits and then specifically */
102 /* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
103 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HPTEFLAGS)
105 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
107 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY)
109 /* __pgprot defined in asm-ppc64/page.h */
110 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
112 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
113 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
114 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
115 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
116 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
117 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
118 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
119 #define PAGE_KERNEL_CI __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
120 _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
121 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
123 #define PAGE_AGP __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
124 #define HAVE_PAGE_AGP
127 * This bit in a hardware PTE indicates that the page is *not* executable.
129 #define HW_NO_EXEC _PAGE_EXEC
132 * POWER4 and newer have per page execute protection, older chips can only
133 * do this on a segment (256MB) basis.
135 * Also, write permissions imply read permissions.
136 * This is the closest we can get..
138 * Note due to the way vm flags are laid out, the bits are XWR
140 #define __P000 PAGE_NONE
141 #define __P001 PAGE_READONLY
142 #define __P010 PAGE_COPY
143 #define __P011 PAGE_COPY
144 #define __P100 PAGE_READONLY_X
145 #define __P101 PAGE_READONLY_X
146 #define __P110 PAGE_COPY_X
147 #define __P111 PAGE_COPY_X
149 #define __S000 PAGE_NONE
150 #define __S001 PAGE_READONLY
151 #define __S010 PAGE_SHARED
152 #define __S011 PAGE_SHARED
153 #define __S100 PAGE_READONLY_X
154 #define __S101 PAGE_READONLY_X
155 #define __S110 PAGE_SHARED_X
156 #define __S111 PAGE_SHARED_X
161 * ZERO_PAGE is a global shared page that is always zero: used
162 * for zero-mapped memory areas etc..
164 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
165 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
166 #endif /* __ASSEMBLY__ */
168 /* shift to put page number into pte */
169 #define PTE_SHIFT (17)
171 /* We allow 2^41 bytes of real memory, so we need 29 bits in the PMD
172 * to give the PTE page number. The bottom two bits are for flags. */
173 #define PMD_TO_PTEPAGE_SHIFT (2)
175 #ifdef CONFIG_HUGETLB_PAGE
178 int hash_huge_page(struct mm_struct *mm, unsigned long access,
179 unsigned long ea, unsigned long vsid, int local);
181 void hugetlb_mm_free_pgd(struct mm_struct *mm);
182 #endif /* __ASSEMBLY__ */
184 #define HAVE_ARCH_UNMAPPED_AREA
185 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
188 #define hash_huge_page(mm,a,ea,vsid,local) -1
189 #define hugetlb_mm_free_pgd(mm) do {} while (0)
196 * Conversion functions: convert a page and protection to a page entry,
197 * and a page entry and page directory to the page they refer to.
199 * mk_pte takes a (struct page *) as input
201 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
203 #define pfn_pte(pfn,pgprot) \
206 pte_val(pte) = ((unsigned long)(pfn) << PTE_SHIFT) | \
207 pgprot_val(pgprot); \
211 #define pte_modify(_pte, newprot) \
212 (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
214 #define pte_none(pte) ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
215 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
217 /* pte_clear moved to later in this file */
219 #define pte_pfn(x) ((unsigned long)((pte_val(x) >> PTE_SHIFT)))
220 #define pte_page(x) pfn_to_page(pte_pfn(x))
222 #define pmd_set(pmdp, ptep) \
223 (pmd_val(*(pmdp)) = (__ba_to_bpn(ptep) << PMD_TO_PTEPAGE_SHIFT))
224 #define pmd_none(pmd) (!pmd_val(pmd))
225 #define pmd_bad(pmd) (pmd_val(pmd) == 0)
226 #define pmd_present(pmd) (pmd_val(pmd) != 0)
227 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0)
228 #define pmd_page_kernel(pmd) \
229 (__bpn_to_ba(pmd_val(pmd) >> PMD_TO_PTEPAGE_SHIFT))
230 #define pmd_page(pmd) virt_to_page(pmd_page_kernel(pmd))
232 #define pud_set(pudp, pmdp) (pud_val(*(pudp)) = (__ba_to_bpn(pmdp)))
233 #define pud_none(pud) (!pud_val(pud))
234 #define pud_bad(pud) ((pud_val(pud)) == 0UL)
235 #define pud_present(pud) (pud_val(pud) != 0UL)
236 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
237 #define pud_page(pud) (__bpn_to_ba(pud_val(pud)))
240 * Find an entry in a page-table-directory. We combine the address region
241 * (the high order N bits) and the pgd portion of the address.
243 /* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
244 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x7ff)
246 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
248 /* Find an entry in the second-level page table.. */
249 #define pmd_offset(pudp,addr) \
250 ((pmd_t *) pud_page(*(pudp)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
252 /* Find an entry in the third-level page table.. */
253 #define pte_offset_kernel(dir,addr) \
254 ((pte_t *) pmd_page_kernel(*(dir)) \
255 + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
257 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
258 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
259 #define pte_unmap(pte) do { } while(0)
260 #define pte_unmap_nested(pte) do { } while(0)
262 /* to find an entry in a kernel page-table-directory */
263 /* This now only contains the vmalloc pages */
264 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
266 /* to find an entry in the ioremap page-table-directory */
267 #define pgd_offset_i(address) (ioremap_pgd + pgd_index(address))
269 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
272 * The following only work if pte_present() is true.
273 * Undefined behaviour if not..
275 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER;}
276 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
277 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC;}
278 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
279 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
280 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
281 static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE;}
283 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
284 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
286 static inline pte_t pte_rdprotect(pte_t pte) {
287 pte_val(pte) &= ~_PAGE_USER; return pte; }
288 static inline pte_t pte_exprotect(pte_t pte) {
289 pte_val(pte) &= ~_PAGE_EXEC; return pte; }
290 static inline pte_t pte_wrprotect(pte_t pte) {
291 pte_val(pte) &= ~(_PAGE_RW); return pte; }
292 static inline pte_t pte_mkclean(pte_t pte) {
293 pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
294 static inline pte_t pte_mkold(pte_t pte) {
295 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
297 static inline pte_t pte_mkread(pte_t pte) {
298 pte_val(pte) |= _PAGE_USER; return pte; }
299 static inline pte_t pte_mkexec(pte_t pte) {
300 pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
301 static inline pte_t pte_mkwrite(pte_t pte) {
302 pte_val(pte) |= _PAGE_RW; return pte; }
303 static inline pte_t pte_mkdirty(pte_t pte) {
304 pte_val(pte) |= _PAGE_DIRTY; return pte; }
305 static inline pte_t pte_mkyoung(pte_t pte) {
306 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
307 static inline pte_t pte_mkhuge(pte_t pte) {
308 pte_val(pte) |= _PAGE_HUGE; return pte; }
310 /* Atomic PTE updates */
311 static inline unsigned long pte_update(pte_t *p, unsigned long clr)
313 unsigned long old, tmp;
315 __asm__ __volatile__(
316 "1: ldarx %0,0,%3 # pte_update\n\
322 : "=&r" (old), "=&r" (tmp), "=m" (*p)
323 : "r" (p), "r" (clr), "m" (*p), "i" (_PAGE_BUSY)
328 /* PTE updating functions, this function puts the PTE in the
329 * batch, doesn't actually triggers the hash flush immediately,
330 * you need to call flush_tlb_pending() to do that.
332 extern void hpte_update(struct mm_struct *mm, unsigned long addr, unsigned long pte,
335 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
339 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
341 old = pte_update(ptep, _PAGE_ACCESSED);
342 if (old & _PAGE_HASHPTE) {
343 hpte_update(mm, addr, old, 0);
346 return (old & _PAGE_ACCESSED) != 0;
348 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
349 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
352 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
357 * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
358 * moment we always flush but we need to fix hpte_update and test if the
359 * optimisation is worth it.
361 static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
365 if ((pte_val(*ptep) & _PAGE_DIRTY) == 0)
367 old = pte_update(ptep, _PAGE_DIRTY);
368 if (old & _PAGE_HASHPTE)
369 hpte_update(mm, addr, old, 0);
370 return (old & _PAGE_DIRTY) != 0;
372 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
373 #define ptep_test_and_clear_dirty(__vma, __addr, __ptep) \
376 __r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
380 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
381 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
385 if ((pte_val(*ptep) & _PAGE_RW) == 0)
387 old = pte_update(ptep, _PAGE_RW);
388 if (old & _PAGE_HASHPTE)
389 hpte_update(mm, addr, old, 0);
393 * We currently remove entries from the hashtable regardless of whether
394 * the entry was young or dirty. The generic routines only flush if the
395 * entry was young or dirty which is not good enough.
397 * We should be more intelligent about this but for the moment we override
398 * these functions and force a tlb flush unconditionally
400 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
401 #define ptep_clear_flush_young(__vma, __address, __ptep) \
403 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
408 #define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
409 #define ptep_clear_flush_dirty(__vma, __address, __ptep) \
411 int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
413 flush_tlb_page(__vma, __address); \
417 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
418 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
420 unsigned long old = pte_update(ptep, ~0UL);
422 if (old & _PAGE_HASHPTE)
423 hpte_update(mm, addr, old, 0);
427 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t * ptep)
429 unsigned long old = pte_update(ptep, ~0UL);
431 if (old & _PAGE_HASHPTE)
432 hpte_update(mm, addr, old, 0);
436 * set_pte stores a linux PTE into the linux page table.
438 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
439 pte_t *ptep, pte_t pte)
441 if (pte_present(*ptep)) {
442 pte_clear(mm, addr, ptep);
445 *ptep = __pte(pte_val(pte)) & ~_PAGE_HPTEFLAGS;
448 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
449 * function doesn't need to flush the hash entry
451 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
452 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
454 unsigned long bits = pte_val(entry) &
455 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
456 unsigned long old, tmp;
458 __asm__ __volatile__(
465 :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
466 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
469 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
471 __ptep_set_access_flags(__ptep, __entry, __dirty); \
472 flush_tlb_page_nohash(__vma, __address); \
476 * Macro to mark a page protection value as "uncacheable".
478 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
481 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
482 unsigned long size, pgprot_t vma_prot);
483 #define __HAVE_PHYS_MEM_ACCESS_PROT
485 #define __HAVE_ARCH_PTE_SAME
486 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
488 extern unsigned long ioremap_bot, ioremap_base;
490 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
491 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
493 #define pte_ERROR(e) \
494 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
495 #define pmd_ERROR(e) \
496 printk("%s:%d: bad pmd %08x.\n", __FILE__, __LINE__, pmd_val(e))
497 #define pgd_ERROR(e) \
498 printk("%s:%d: bad pgd %08x.\n", __FILE__, __LINE__, pgd_val(e))
500 extern pgd_t swapper_pg_dir[1024];
501 extern pgd_t ioremap_dir[1024];
503 extern void paging_init(void);
506 * Because the huge pgtables are only 2 level, they can take
507 * at most around 4M, much less than one hugepage which the
508 * process is presumably entitled to use. So we don't bother
509 * freeing up the pagetables on unmap, and wait until
510 * destroy_context() to clean up the lot.
512 #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) \
516 * This gets called at the end of handling a page fault, when
517 * the kernel has put a new PTE into the page table for the process.
518 * We use it to put a corresponding HPTE into the hash table
519 * ahead of time, instead of waiting for the inevitable extra
520 * hash-table miss exception.
522 struct vm_area_struct;
523 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
525 /* Encode and de-code a swap entry */
526 #define __swp_type(entry) (((entry).val >> 1) & 0x3f)
527 #define __swp_offset(entry) ((entry).val >> 8)
528 #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
529 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> PTE_SHIFT })
530 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << PTE_SHIFT })
531 #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
532 #define pgoff_to_pte(off) ((pte_t) {((off) << PTE_SHIFT)|_PAGE_FILE})
533 #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT)
536 * kern_addr_valid is intended to indicate whether an address is a valid
537 * kernel address. Most 32-bit archs define it as always true (like this)
538 * but most 64-bit archs actually perform a test. What should we do here?
539 * The only use is in fs/ncpfs/dir.c
541 #define kern_addr_valid(addr) (1)
543 #define io_remap_page_range(vma, vaddr, paddr, size, prot) \
544 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
546 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
547 remap_pfn_range(vma, vaddr, pfn, size, prot)
549 #define MK_IOSPACE_PFN(space, pfn) (pfn)
550 #define GET_IOSPACE(pfn) 0
551 #define GET_PFN(pfn) (pfn)
553 void pgtable_cache_init(void);
555 extern void hpte_init_native(void);
556 extern void hpte_init_lpar(void);
557 extern void hpte_init_iSeries(void);
559 /* imalloc region types */
560 #define IM_REGION_UNUSED 0x1
561 #define IM_REGION_SUBSET 0x2
562 #define IM_REGION_EXISTS 0x4
563 #define IM_REGION_OVERLAP 0x8
564 #define IM_REGION_SUPERSET 0x10
566 extern struct vm_struct * im_get_free_area(unsigned long size);
567 extern struct vm_struct * im_get_area(unsigned long v_addr, unsigned long size,
569 unsigned long im_free(void *addr);
571 extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
572 unsigned long va, unsigned long prpn,
573 int secondary, unsigned long hpteflags,
574 int bolted, int large);
576 extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
577 unsigned long prpn, int secondary,
578 unsigned long hpteflags, int bolted, int large);
581 * find_linux_pte returns the address of a linux pte for a given
582 * effective address and directory. If not found, it returns zero.
584 static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
592 pg = pgdir + pgd_index(ea);
593 if (!pgd_none(*pg)) {
594 pu = pud_offset(pg, ea);
595 if (!pud_none(*pu)) {
596 pm = pmd_offset(pu, ea);
597 if (pmd_present(*pm)) {
598 pt = pte_offset_kernel(pm, ea);
600 if (!pte_present(pte))
609 #include <asm-generic/pgtable.h>
611 #endif /* __ASSEMBLY__ */
613 #endif /* _PPC64_PGTABLE_H */