2 * PowerPC memory management structures
9 #include <linux/config.h>
14 * Define physical address type. Machines using split size
15 * virtual/physical addressing like 32-bit virtual / 36-bit
16 * physical need a larger than native word size type. -Matt
18 #ifndef CONFIG_PHYS_64BIT
19 typedef unsigned long phys_addr_t;
20 #define PHYS_FMT "%.8lx"
22 typedef unsigned long long phys_addr_t;
23 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
24 #define PHYS_FMT "%16Lx"
29 unsigned long vdso_base;
32 /* Hardware Page Table Entry */
34 unsigned long v:1; /* Entry is valid */
35 unsigned long vsid:24; /* Virtual segment identifier */
36 unsigned long h:1; /* Hash algorithm indicator */
37 unsigned long api:6; /* Abbreviated page index */
38 unsigned long rpn:20; /* Real (physical) page number */
39 unsigned long :3; /* Unused */
40 unsigned long r:1; /* Referenced */
41 unsigned long c:1; /* Changed */
42 unsigned long w:1; /* Write-thru cache mode */
43 unsigned long i:1; /* Cache inhibited */
44 unsigned long m:1; /* Memory coherence */
45 unsigned long g:1; /* Guarded */
46 unsigned long :1; /* Unused */
47 unsigned long pp:2; /* Page protection */
50 /* Values for PP (assumes Ks=0, Kp=1) */
51 #define PP_RWXX 0 /* Supervisor read/write, User none */
52 #define PP_RWRX 1 /* Supervisor read/write, User read */
53 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
54 #define PP_RXRX 3 /* Supervisor read, User read */
56 /* Segment Register */
57 typedef struct _SEGREG {
58 unsigned long t:1; /* Normal or I/O type */
59 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
60 unsigned long kp:1; /* User 'key' (normally 1) */
61 unsigned long n:1; /* No-execute */
62 unsigned long :4; /* Unused */
63 unsigned long vsid:24; /* Virtual Segment Identifier */
66 /* Block Address Translation (BAT) Registers */
67 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
68 unsigned long bepi:15; /* Effective page index (virtual address) */
69 unsigned long :8; /* unused */
71 unsigned long i:1; /* Cache inhibit */
72 unsigned long m:1; /* Memory coherence */
73 unsigned long ks:1; /* Supervisor key (normally 0) */
74 unsigned long kp:1; /* User key (normally 1) */
75 unsigned long pp:2; /* Page access protections */
78 typedef struct _BATU { /* Upper part of BAT (all except 601) */
79 unsigned long bepi:15; /* Effective page index (virtual address) */
80 unsigned long :4; /* Unused */
81 unsigned long bl:11; /* Block size mask */
82 unsigned long vs:1; /* Supervisor valid */
83 unsigned long vp:1; /* User valid */
86 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
87 unsigned long brpn:15; /* Real page index (physical address) */
88 unsigned long :10; /* Unused */
89 unsigned long v:1; /* Valid bit */
90 unsigned long bl:6; /* Block size mask */
93 typedef struct _BATL { /* Lower part of BAT (all except 601) */
94 unsigned long brpn:15; /* Real page index (physical address) */
95 unsigned long :10; /* Unused */
96 unsigned long w:1; /* Write-thru cache */
97 unsigned long i:1; /* Cache inhibit */
98 unsigned long m:1; /* Memory coherence */
99 unsigned long g:1; /* Guarded (MBZ in IBAT) */
100 unsigned long :1; /* Unused */
101 unsigned long pp:2; /* Page access protections */
104 typedef struct _BAT {
105 BATU batu; /* Upper register */
106 BATL batl; /* Lower register */
109 typedef struct _P601_BAT {
110 P601_BATU batu; /* Upper register */
111 P601_BATL batl; /* Lower register */
114 #endif /* __ASSEMBLY__ */
116 /* Block size masks */
117 #define BL_128K 0x000
118 #define BL_256K 0x001
119 #define BL_512K 0x003
127 #define BL_128M 0x3FF
128 #define BL_256M 0x7FF
130 /* BAT Access Protection */
131 #define BPP_XX 0x00 /* No access */
132 #define BPP_RX 0x01 /* Read only */
133 #define BPP_RW 0x02 /* Read/write */
135 /* Control/status registers for the MPC8xx.
136 * A write operation to these registers causes serialized access.
137 * During software tablewalk, the registers used perform mask/shift-add
138 * operations when written/read. A TLB entry is created when the Mx_RPN
139 * is written, and the contents of several registers are used to
142 #define SPRN_MI_CTR 784 /* Instruction TLB control register */
143 #define MI_GPM 0x80000000 /* Set domain manager mode */
144 #define MI_PPM 0x40000000 /* Set subpage protection */
145 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
146 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
147 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
148 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
149 #define MI_RESETVAL 0x00000000 /* Value of register at reset */
151 /* These are the Ks and Kp from the PowerPC books. For proper operation,
154 #define SPRN_MI_AP 786
155 #define MI_Ks 0x80000000 /* Should not be set */
156 #define MI_Kp 0x40000000 /* Should always be set */
158 /* The effective page number register. When read, contains the information
159 * about the last instruction TLB miss. When MI_RPN is written, bits in
160 * this register are used to create the TLB entry.
162 #define SPRN_MI_EPN 787
163 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
164 #define MI_EVALID 0x00000200 /* Entry is valid */
165 #define MI_ASIDMASK 0x0000000f /* ASID match value */
166 /* Reset value is undefined */
168 /* A "level 1" or "segment" or whatever you want to call it register.
169 * For the instruction TLB, it contains bits that get loaded into the
170 * TLB entry when the MI_RPN is written.
172 #define SPRN_MI_TWC 789
173 #define MI_APG 0x000001e0 /* Access protection group (0) */
174 #define MI_GUARDED 0x00000010 /* Guarded storage */
175 #define MI_PSMASK 0x0000000c /* Mask of page size bits */
176 #define MI_PS8MEG 0x0000000c /* 8M page size */
177 #define MI_PS512K 0x00000004 /* 512K page size */
178 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
179 #define MI_SVALID 0x00000001 /* Segment entry is valid */
180 /* Reset value is undefined */
182 /* Real page number. Defined by the pte. Writing this register
183 * causes a TLB entry to be created for the instruction TLB, using
184 * additional information from the MI_EPN, and MI_TWC registers.
186 #define SPRN_MI_RPN 790
188 /* Define an RPN value for mapping kernel memory to large virtual
189 * pages for boot initialization. This has real page number of 0,
190 * large page size, shared page, cache enabled, and valid.
191 * Also mark all subpages valid and write access.
193 #define MI_BOOTINIT 0x000001fd
195 #define SPRN_MD_CTR 792 /* Data TLB control register */
196 #define MD_GPM 0x80000000 /* Set domain manager mode */
197 #define MD_PPM 0x40000000 /* Set subpage protection */
198 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
199 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
200 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
201 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
202 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
203 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
204 #define MD_RESETVAL 0x04000000 /* Value of register at reset */
206 #define SPRN_M_CASID 793 /* Address space ID (context) to match */
207 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
210 /* These are the Ks and Kp from the PowerPC books. For proper operation,
213 #define SPRN_MD_AP 794
214 #define MD_Ks 0x80000000 /* Should not be set */
215 #define MD_Kp 0x40000000 /* Should always be set */
217 /* The effective page number register. When read, contains the information
218 * about the last instruction TLB miss. When MD_RPN is written, bits in
219 * this register are used to create the TLB entry.
221 #define SPRN_MD_EPN 795
222 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
223 #define MD_EVALID 0x00000200 /* Entry is valid */
224 #define MD_ASIDMASK 0x0000000f /* ASID match value */
225 /* Reset value is undefined */
227 /* The pointer to the base address of the first level page table.
228 * During a software tablewalk, reading this register provides the address
229 * of the entry associated with MD_EPN.
231 #define SPRN_M_TWB 796
232 #define M_L1TB 0xfffff000 /* Level 1 table base address */
233 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
234 /* Reset value is undefined */
236 /* A "level 1" or "segment" or whatever you want to call it register.
237 * For the data TLB, it contains bits that get loaded into the TLB entry
238 * when the MD_RPN is written. It is also provides the hardware assist
239 * for finding the PTE address during software tablewalk.
241 #define SPRN_MD_TWC 797
242 #define MD_L2TB 0xfffff000 /* Level 2 table base address */
243 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
244 #define MD_APG 0x000001e0 /* Access protection group (0) */
245 #define MD_GUARDED 0x00000010 /* Guarded storage */
246 #define MD_PSMASK 0x0000000c /* Mask of page size bits */
247 #define MD_PS8MEG 0x0000000c /* 8M page size */
248 #define MD_PS512K 0x00000004 /* 512K page size */
249 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
250 #define MD_WT 0x00000002 /* Use writethrough page attribute */
251 #define MD_SVALID 0x00000001 /* Segment entry is valid */
252 /* Reset value is undefined */
255 /* Real page number. Defined by the pte. Writing this register
256 * causes a TLB entry to be created for the data TLB, using
257 * additional information from the MD_EPN, and MD_TWC registers.
259 #define SPRN_MD_RPN 798
261 /* This is a temporary storage register that could be used to save
262 * a processor working register during a tablewalk.
264 #define SPRN_M_TW 799
267 * At present, all PowerPC 400-class processors share a similar TLB
268 * architecture. The instruction and data sides share a unified,
269 * 64-entry, fully-associative TLB which is maintained totally under
270 * software control. In addition, the instruction side has a
271 * hardware-managed, 4-entry, fully- associative TLB which serves as a
272 * first level to the shared TLB. These two TLBs are known as the UTLB
273 * and ITLB, respectively.
276 #define PPC4XX_TLB_SIZE 64
279 * TLB entries are defined by a "high" tag portion and a "low" data
280 * portion. On all architectures, the data portion is 32-bits.
282 * TLB entries are managed entirely under software control by reading,
283 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
290 #define TLB_DATA TLB_LO
291 #define TLB_TAG TLB_HI
295 #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
296 #define TLB_PAGESZ_MASK 0x00000380
297 #define TLB_PAGESZ(x) (((x) & 0x7) << 7)
302 #define PAGESZ_256K 4
306 #define TLB_VALID 0x00000040 /* Entry is valid */
310 #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
311 #define TLB_PERM_MASK 0x00000300
312 #define TLB_EX 0x00000200 /* Instruction execution allowed */
313 #define TLB_WR 0x00000100 /* Writes permitted */
314 #define TLB_ZSEL_MASK 0x000000F0
315 #define TLB_ZSEL(x) (((x) & 0xF) << 4)
316 #define TLB_ATTR_MASK 0x0000000F
317 #define TLB_W 0x00000008 /* Caching is write-through */
318 #define TLB_I 0x00000004 /* Caching is inhibited */
319 #define TLB_M 0x00000002 /* Memory is coherent */
320 #define TLB_G 0x00000001 /* Memory is guarded from prefetch */
325 #define PPC44x_MMUCR_TID 0x000000ff
326 #define PPC44x_MMUCR_STS 0x00010000
328 #define PPC44x_TLB_PAGEID 0
329 #define PPC44x_TLB_XLAT 1
330 #define PPC44x_TLB_ATTRIB 2
332 /* Page identification fields */
333 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
334 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
335 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
336 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
337 #define PPC44x_TLB_4K 0x00000010
338 #define PPC44x_TLB_16K 0x00000020
339 #define PPC44x_TLB_64K 0x00000030
340 #define PPC44x_TLB_256K 0x00000040
341 #define PPC44x_TLB_1M 0x00000050
342 #define PPC44x_TLB_16M 0x00000070
343 #define PPC44x_TLB_256M 0x00000090
345 /* Translation fields */
346 #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
347 #define PPC44x_TLB_ERPN_MASK 0x0000000f
349 /* Storage attribute and access control fields */
350 #define PPC44x_TLB_ATTR_MASK 0x0000ff80
351 #define PPC44x_TLB_U0 0x00008000 /* User 0 */
352 #define PPC44x_TLB_U1 0x00004000 /* User 1 */
353 #define PPC44x_TLB_U2 0x00002000 /* User 2 */
354 #define PPC44x_TLB_U3 0x00001000 /* User 3 */
355 #define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
356 #define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
357 #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
358 #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
359 #define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
361 #define PPC44x_TLB_PERM_MASK 0x0000003f
362 #define PPC44x_TLB_UX 0x00000020 /* User execution */
363 #define PPC44x_TLB_UW 0x00000010 /* User write */
364 #define PPC44x_TLB_UR 0x00000008 /* User read */
365 #define PPC44x_TLB_SX 0x00000004 /* Super execution */
366 #define PPC44x_TLB_SW 0x00000002 /* Super write */
367 #define PPC44x_TLB_SR 0x00000001 /* Super read */
369 /* Book-E defined page sizes */
370 #define BOOKE_PAGESZ_1K 0
371 #define BOOKE_PAGESZ_4K 1
372 #define BOOKE_PAGESZ_16K 2
373 #define BOOKE_PAGESZ_64K 3
374 #define BOOKE_PAGESZ_256K 4
375 #define BOOKE_PAGESZ_1M 5
376 #define BOOKE_PAGESZ_4M 6
377 #define BOOKE_PAGESZ_16M 7
378 #define BOOKE_PAGESZ_64M 8
379 #define BOOKE_PAGESZ_256M 9
380 #define BOOKE_PAGESZ_1GB 10
381 #define BOOKE_PAGESZ_4GB 11
382 #define BOOKE_PAGESZ_16GB 12
383 #define BOOKE_PAGESZ_64GB 13
384 #define BOOKE_PAGESZ_256GB 14
385 #define BOOKE_PAGESZ_1TB 15
388 * Freescale Book-E MMU support
391 #define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
392 #define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
393 #define MAS0_NV(x) ((x) & 0x00000FFF)
395 #define MAS1_VALID 0x80000000
396 #define MAS1_IPROT 0x40000000
397 #define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
398 #define MAS1_TS 0x00001000
399 #define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
401 #define MAS2_EPN 0xFFFFF000
402 #define MAS2_X0 0x00000040
403 #define MAS2_X1 0x00000020
404 #define MAS2_W 0x00000010
405 #define MAS2_I 0x00000008
406 #define MAS2_M 0x00000004
407 #define MAS2_G 0x00000002
408 #define MAS2_E 0x00000001
410 #define MAS3_RPN 0xFFFFF000
411 #define MAS3_U0 0x00000200
412 #define MAS3_U1 0x00000100
413 #define MAS3_U2 0x00000080
414 #define MAS3_U3 0x00000040
415 #define MAS3_UX 0x00000020
416 #define MAS3_SX 0x00000010
417 #define MAS3_UW 0x00000008
418 #define MAS3_SW 0x00000004
419 #define MAS3_UR 0x00000002
420 #define MAS3_SR 0x00000001
422 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
423 #define MAS4_TIDDSEL 0x000F0000
424 #define MAS4_TSIZED(x) MAS1_TSIZE(x)
425 #define MAS4_X0D 0x00000040
426 #define MAS4_X1D 0x00000020
427 #define MAS4_WD 0x00000010
428 #define MAS4_ID 0x00000008
429 #define MAS4_MD 0x00000004
430 #define MAS4_GD 0x00000002
431 #define MAS4_ED 0x00000001
433 #define MAS6_SPID0 0x3FFF0000
434 #define MAS6_SPID1 0x00007FFE
435 #define MAS6_SAS 0x00000001
436 #define MAS6_SPID MAS6_SPID0
438 #define MAS7_RPN 0xFFFFFFFF
440 #endif /* _PPC_MMU_H_ */
441 #endif /* __KERNEL__ */