1 #ifndef _ASM_POWERPC_SYNCH_H
2 #define _ASM_POWERPC_SYNCH_H
6 #define __SUBARCH_HAS_LWSYNC
9 #ifdef __SUBARCH_HAS_LWSYNC
10 # define LWSYNC lwsync
17 * Arguably the bitops and *xchg operations don't imply any memory barrier
18 * or SMP ordering, but in fact a lot of drivers expect them to imply
19 * both, since they do on x86 cpus.
22 #define EIEIO_ON_SMP "eieio\n"
23 #define ISYNC_ON_SMP "\n\tisync"
24 #define SYNC_ON_SMP __stringify(LWSYNC) "\n"
31 static inline void eieio(void)
33 __asm__ __volatile__ ("eieio" : : : "memory");
36 static inline void isync(void)
38 __asm__ __volatile__ ("isync" : : : "memory");
42 #define eieio_on_smp() eieio()
43 #define isync_on_smp() isync()
45 #define eieio_on_smp() __asm__ __volatile__("": : :"memory")
46 #define isync_on_smp() __asm__ __volatile__("": : :"memory")
49 #endif /* __KERNEL__ */
50 #endif /* _ASM_POWERPC_SYNCH_H */