2 * SPU core / file system interface and HW structures
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/config.h>
28 #include <linux/kref.h>
29 #include <linux/workqueue.h>
31 #define LS_ORDER (6) /* 256 kb */
33 #define LS_SIZE (PAGE_SIZE << LS_ORDER)
34 #define LS_ADDR_MASK (LS_SIZE - 1)
36 #define MFC_PUT_CMD 0x20
37 #define MFC_PUTS_CMD 0x28
38 #define MFC_PUTR_CMD 0x30
39 #define MFC_PUTF_CMD 0x22
40 #define MFC_PUTB_CMD 0x21
41 #define MFC_PUTFS_CMD 0x2A
42 #define MFC_PUTBS_CMD 0x29
43 #define MFC_PUTRF_CMD 0x32
44 #define MFC_PUTRB_CMD 0x31
45 #define MFC_PUTL_CMD 0x24
46 #define MFC_PUTRL_CMD 0x34
47 #define MFC_PUTLF_CMD 0x26
48 #define MFC_PUTLB_CMD 0x25
49 #define MFC_PUTRLF_CMD 0x36
50 #define MFC_PUTRLB_CMD 0x35
52 #define MFC_GET_CMD 0x40
53 #define MFC_GETS_CMD 0x48
54 #define MFC_GETF_CMD 0x42
55 #define MFC_GETB_CMD 0x41
56 #define MFC_GETFS_CMD 0x4A
57 #define MFC_GETBS_CMD 0x49
58 #define MFC_GETL_CMD 0x44
59 #define MFC_GETLF_CMD 0x46
60 #define MFC_GETLB_CMD 0x45
62 #define MFC_SDCRT_CMD 0x80
63 #define MFC_SDCRTST_CMD 0x81
64 #define MFC_SDCRZ_CMD 0x89
65 #define MFC_SDCRS_CMD 0x8D
66 #define MFC_SDCRF_CMD 0x8F
68 #define MFC_GETLLAR_CMD 0xD0
69 #define MFC_PUTLLC_CMD 0xB4
70 #define MFC_PUTLLUC_CMD 0xB0
71 #define MFC_PUTQLLUC_CMD 0xB8
72 #define MFC_SNDSIG_CMD 0xA0
73 #define MFC_SNDSIGB_CMD 0xA1
74 #define MFC_SNDSIGF_CMD 0xA2
75 #define MFC_BARRIER_CMD 0xC0
76 #define MFC_EIEIO_CMD 0xC8
77 #define MFC_SYNC_CMD 0xCC
79 #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
80 #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
81 #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
82 #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
83 #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
84 #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
85 #define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
86 #define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
88 #define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
90 /* Events for Channels 0-2 */
91 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
92 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
93 #define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
94 #define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
95 #define MFC_DECREMENTER_EVENT 0x00000020
96 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
97 #define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
98 #define MFC_SIGNAL_2_EVENT 0x00000100
99 #define MFC_SIGNAL_1_EVENT 0x00000200
100 #define MFC_LLR_LOST_EVENT 0x00000400
101 #define MFC_PRIV_ATTN_EVENT 0x00000800
102 #define MFC_MULTI_SRC_EVENT 0x00001000
104 /* Flags indicating progress during context switch. */
105 #define SPU_CONTEXT_SWITCH_PENDING_nr 0UL
106 #define SPU_CONTEXT_SWITCH_ACTIVE_nr 1UL
107 #define SPU_CONTEXT_SWITCH_PENDING (1UL << SPU_CONTEXT_SWITCH_PENDING_nr)
108 #define SPU_CONTEXT_SWITCH_ACTIVE (1UL << SPU_CONTEXT_SWITCH_ACTIVE_nr)
115 unsigned long local_store_phys;
117 struct spu_problem __iomem *problem;
118 struct spu_priv1 __iomem *priv1;
119 struct spu_priv2 __iomem *priv2;
120 struct list_head list;
121 struct list_head sched_list;
130 unsigned int slb_replace;
131 struct mm_struct *mm;
132 struct spu_context *ctx;
133 struct spu_runqueue *rq;
134 unsigned long long timestamp;
138 spinlock_t register_lock;
141 void (* wbox_callback)(struct spu *spu);
142 void (* ibox_callback)(struct spu *spu);
143 void (* stop_callback)(struct spu *spu);
150 struct spu *spu_alloc(void);
151 void spu_free(struct spu *spu);
152 int spu_irq_class_0_bottom(struct spu *spu);
153 int spu_irq_class_1_bottom(struct spu *spu);
155 extern struct spufs_calls {
156 asmlinkage long (*create_thread)(const char __user *name,
157 unsigned int flags, mode_t mode);
158 asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
159 __u32 __user *ustatus);
160 struct module *owner;
163 #ifdef CONFIG_SPU_FS_MODULE
164 int register_spu_syscalls(struct spufs_calls *calls);
165 void unregister_spu_syscalls(struct spufs_calls *calls);
167 static inline int register_spu_syscalls(struct spufs_calls *calls)
171 static inline void unregister_spu_syscalls(struct spufs_calls *calls)
178 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
181 union mfc_tag_size_class_cmd {
204 #define MS_SYNC_PENDING 1L
205 u64 spc_mssync_RW; /* 0x0000 */
206 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
209 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
210 u32 mfc_lsa_W; /* 0x3004 */
211 u64 mfc_ea_W; /* 0x3008 */
212 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
213 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
214 u32 dma_qstatus_R; /* 0x3104 */
215 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
216 u32 dma_querytype_RW; /* 0x3204 */
217 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
218 u32 dma_querymask_RW; /* 0x321c */
219 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
220 u32 dma_tagstatus_R; /* 0x322c */
221 #define DMA_TAGSTATUS_INTR_ANY 1u
222 #define DMA_TAGSTATUS_INTR_ALL 2u
223 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
225 /* SPU Control Area */
226 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
227 u32 pu_mb_R; /* 0x4004 */
228 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
229 u32 spu_mb_W; /* 0x400c */
230 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
231 u32 mb_stat_R; /* 0x4014 */
232 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
233 u32 spu_runcntl_RW; /* 0x401c */
234 #define SPU_RUNCNTL_STOP 0L
235 #define SPU_RUNCNTL_RUNNABLE 1L
236 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
237 u32 spu_status_R; /* 0x4024 */
238 #define SPU_STOP_STATUS_SHIFT 16
239 #define SPU_STATUS_STOPPED 0x0
240 #define SPU_STATUS_RUNNING 0x1
241 #define SPU_STATUS_STOPPED_BY_STOP 0x2
242 #define SPU_STATUS_STOPPED_BY_HALT 0x4
243 #define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
244 #define SPU_STATUS_SINGLE_STEP 0x10
245 #define SPU_STATUS_INVALID_INSTR 0x20
246 #define SPU_STATUS_INVALID_CH 0x40
247 #define SPU_STATUS_ISOLATED_STATE 0x80
248 #define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
249 #define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
250 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
251 u32 spu_spe_R; /* 0x402c */
252 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
253 u32 spu_npc_RW; /* 0x4034 */
254 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
256 /* Signal Notification Area */
257 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
258 u32 signal_notify1; /* 0x1400c */
259 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
260 u32 signal_notify2; /* 0x1c00c */
261 } __attribute__ ((aligned(0x20000)));
263 /* SPU Privilege 2 State Area */
266 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
268 /* SLB Management Registers */
269 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
270 u64 slb_index_W; /* 0x1108 */
271 #define SLB_INDEX_MASK 0x7L
272 u64 slb_esid_RW; /* 0x1110 */
273 u64 slb_vsid_RW; /* 0x1118 */
274 #define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
275 #define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
276 #define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
277 #define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
278 #define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
279 #define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
280 #define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
281 #define SLB_VSID_4K_PAGE (0x0 << 8)
282 #define SLB_VSID_LARGE_PAGE (0x1ull << 8)
283 #define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
284 #define SLB_VSID_CLASS_MASK (0x1ull << 7)
285 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
286 u64 slb_invalidate_entry_W; /* 0x1120 */
287 u64 slb_invalidate_all_W; /* 0x1128 */
288 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
290 /* Context Save / Restore Area */
291 struct mfc_cq_sr spuq[16]; /* 0x2000 */
292 struct mfc_cq_sr puq[8]; /* 0x2200 */
293 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
296 u64 mfc_control_RW; /* 0x3000 */
297 #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
298 #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
299 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
300 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
301 #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
302 #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
303 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
304 #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
305 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
306 #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
307 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
308 #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
309 #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
310 #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
311 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
312 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
313 #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
314 #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
315 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
316 #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
317 #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
318 #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
319 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
321 /* Interrupt Mailbox */
322 u64 puint_mb_R; /* 0x4000 */
323 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
326 u64 spu_privcntl_RW; /* 0x4040 */
327 #define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
328 #define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
329 #define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
330 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
331 #define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
332 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
333 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
334 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
335 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
336 u64 spu_lslr_RW; /* 0x4058 */
337 u64 spu_chnlcntptr_RW; /* 0x4060 */
338 u64 spu_chnlcnt_RW; /* 0x4068 */
339 u64 spu_chnldata_RW; /* 0x4070 */
340 u64 spu_cfg_RW; /* 0x4078 */
341 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
343 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
344 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
345 u64 spu_tag_status_query_RW; /* 0x5008 */
346 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
347 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
348 u64 spu_cmd_buf1_RW; /* 0x5010 */
349 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
350 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
351 u64 spu_cmd_buf2_RW; /* 0x5018 */
352 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
353 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
354 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
355 u64 spu_atomic_status_RW; /* 0x5020 */
356 } __attribute__ ((aligned(0x20000)));
358 /* SPU Privilege 1 State Area */
360 /* Control and Configuration Area */
361 u64 mfc_sr1_RW; /* 0x000 */
362 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
363 #define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
364 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
365 #define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
366 #define MFC_STATE1_RELOCATE_MASK 0x10ull
367 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
368 u64 mfc_lpid_RW; /* 0x008 */
369 u64 spu_idr_RW; /* 0x010 */
370 u64 mfc_vr_RO; /* 0x018 */
371 #define MFC_VERSION_BITS (0xffff << 16)
372 #define MFC_REVISION_BITS (0xffff)
373 #define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
374 #define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
375 u64 spu_vr_RO; /* 0x020 */
376 #define SPU_VERSION_BITS (0xffff << 16)
377 #define SPU_REVISION_BITS (0xffff)
378 #define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
379 #define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
380 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
384 u64 int_mask_class0_RW; /* 0x100 */
385 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
386 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
387 #define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
388 #define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
389 u64 int_mask_class1_RW; /* 0x108 */
390 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
391 #define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
392 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
393 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
394 u64 int_mask_class2_RW; /* 0x110 */
395 #define CLASS2_ENABLE_MAILBOX_INTR 0x1L
396 #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
397 #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
398 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
399 u8 pad_0x118_0x140[0x28]; /* 0x118 */
400 u64 int_stat_class0_RW; /* 0x140 */
401 u64 int_stat_class1_RW; /* 0x148 */
402 u64 int_stat_class2_RW; /* 0x150 */
403 u8 pad_0x158_0x180[0x28]; /* 0x158 */
404 u64 int_route_RW; /* 0x180 */
406 /* Interrupt Routing */
407 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
409 /* Atomic Unit Control Area */
410 u64 mfc_atomic_flush_RW; /* 0x200 */
411 #define mfc_atomic_flush_enable 0x1L
412 u8 pad_0x208_0x280[0x78]; /* 0x208 */
413 u64 resource_allocation_groupID_RW; /* 0x280 */
414 u64 resource_allocation_enable_RW; /* 0x288 */
415 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
417 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
419 u64 smf_sbi_signal_sel; /* 0x3c8 */
420 #define smf_sbi_mask_lsb 56
421 #define smf_sbi_shift (63 - smf_sbi_mask_lsb)
422 #define smf_sbi_mask (0x301LL << smf_sbi_shift)
423 #define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
424 #define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
425 #define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
426 #define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
427 u64 smf_ato_signal_sel; /* 0x3d0 */
428 #define smf_ato_mask_lsb 35
429 #define smf_ato_shift (63 - smf_ato_mask_lsb)
430 #define smf_ato_mask (0x3LL << smf_ato_shift)
431 #define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
432 #define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
433 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
435 /* TLB Management Registers */
436 u64 mfc_sdr_RW; /* 0x400 */
437 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
438 u64 tlb_index_hint_RO; /* 0x500 */
439 u64 tlb_index_W; /* 0x508 */
440 u64 tlb_vpn_RW; /* 0x510 */
441 u64 tlb_rpn_RW; /* 0x518 */
442 u8 pad_0x520_0x540[0x20]; /* 0x520 */
443 u64 tlb_invalidate_entry_W; /* 0x540 */
444 u64 tlb_invalidate_all_W; /* 0x548 */
445 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
447 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
448 u64 smm_hid; /* 0x580 */
449 #define PAGE_SIZE_MASK 0xf000000000000000ull
450 #define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
451 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
453 /* MFC Status/Control Area */
454 u64 mfc_accr_RW; /* 0x600 */
455 #define MFC_ACCR_EA_ACCESS_GET (1 << 0)
456 #define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
457 #define MFC_ACCR_LS_ACCESS_GET (1 << 3)
458 #define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
459 u8 pad_0x608_0x610[0x8]; /* 0x608 */
460 u64 mfc_dsisr_RW; /* 0x610 */
461 #define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
462 #define MFC_DSISR_ACCESS_DENIED (1 << 27)
463 #define MFC_DSISR_ATOMIC (1 << 26)
464 #define MFC_DSISR_ACCESS_PUT (1 << 25)
465 #define MFC_DSISR_ADDR_MATCH (1 << 22)
466 #define MFC_DSISR_LS (1 << 17)
467 #define MFC_DSISR_L (1 << 16)
468 #define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
469 u8 pad_0x618_0x620[0x8]; /* 0x618 */
470 u64 mfc_dar_RW; /* 0x620 */
471 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
473 /* Replacement Management Table (RMT) Area */
474 u64 rmt_index_RW; /* 0x700 */
475 u8 pad_0x708_0x710[0x8]; /* 0x708 */
476 u64 rmt_data1_RW; /* 0x710 */
477 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
479 /* Control/Configuration Registers */
480 u64 mfc_dsir_R; /* 0x800 */
481 #define MFC_DSIR_Q (1 << 31)
482 #define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
483 u64 mfc_lsacr_RW; /* 0x808 */
484 #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
485 #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
486 u64 mfc_lscrr_R; /* 0x810 */
487 #define MFC_LSCRR_Q (1 << 31)
488 #define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
489 #define MFC_LSCRR_QI_SHIFT 32
490 #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
491 u8 pad_0x818_0x820[0x8]; /* 0x818 */
492 u64 mfc_tclass_id_RW; /* 0x820 */
493 #define MFC_TCLASS_ID_ENABLE (1L << 0L)
494 #define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
495 #define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
496 #define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
497 #define MFC_TCLASS_QUOTA_2_SHIFT 8L
498 #define MFC_TCLASS_QUOTA_1_SHIFT 16L
499 #define MFC_TCLASS_QUOTA_0_SHIFT 24L
500 #define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
501 #define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
502 #define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
503 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
505 /* Real Mode Support Registers */
506 u64 mfc_rm_boundary; /* 0x900 */
507 u8 pad_0x908_0x938[0x30]; /* 0x908 */
508 u64 smf_dma_signal_sel; /* 0x938 */
509 #define mfc_dma1_mask_lsb 41
510 #define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
511 #define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
512 #define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
513 #define mfc_dma2_mask_lsb 43
514 #define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
515 #define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
516 #define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
517 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
518 u64 smm_signal_sel; /* 0xa38 */
519 #define smm_sig_mask_lsb 12
520 #define smm_sig_shift (63 - smm_sig_mask_lsb)
521 #define smm_sig_mask (0x3LL << smm_sig_shift)
522 #define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
523 #define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
524 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
526 /* DMA Command Error Area */
527 u64 mfc_cer_R; /* 0xc00 */
528 #define MFC_CER_Q (1 << 31)
529 #define MFC_CER_SPU_QUEUE MFC_CER_Q
530 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
532 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
533 /* DMA Command Error Area */
534 u64 spu_ecc_cntl_RW; /* 0x1000 */
535 #define SPU_ECC_CNTL_E (1ull << 0ull)
536 #define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
537 #define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
538 #define SPU_ECC_CNTL_S (1ull << 1ull)
539 #define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
540 #define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
541 #define SPU_ECC_CNTL_B (1ull << 2ull)
542 #define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
543 #define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
544 #define SPU_ECC_CNTL_I_SHIFT 3ull
545 #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
546 #define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
547 #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
548 #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
549 #define SPU_ECC_CNTL_D (1ull << 5ull)
550 #define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
551 #define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
552 u64 spu_ecc_stat_RW; /* 0x1008 */
553 #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
554 #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
555 #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
556 #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
557 #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
558 #define SPU_ECC_DATA_ERROR (1ull << 5ul)
559 #define SPU_ECC_DMA_ERROR (1ull << 6ul)
560 #define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
561 u64 spu_ecc_addr_RW; /* 0x1010 */
562 u64 spu_err_mask_RW; /* 0x1018 */
563 #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
564 #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
565 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
567 /* SPU Debug-Trace Bus (DTB) Selection Registers */
568 u64 spu_trig0_sel; /* 0x1028 */
569 u64 spu_trig1_sel; /* 0x1030 */
570 u64 spu_trig2_sel; /* 0x1038 */
571 u64 spu_trig3_sel; /* 0x1040 */
572 u64 spu_trace_sel; /* 0x1048 */
573 #define spu_trace_sel_mask 0x1f1fLL
574 #define spu_trace_sel_bus0_bits 0x1000LL
575 #define spu_trace_sel_bus2_bits 0x0010LL
576 u64 spu_event0_sel; /* 0x1050 */
577 u64 spu_event1_sel; /* 0x1058 */
578 u64 spu_event2_sel; /* 0x1060 */
579 u64 spu_event3_sel; /* 0x1068 */
580 u64 spu_trace_cntl; /* 0x1070 */
581 } __attribute__ ((aligned(0x2000)));
583 #endif /* __KERNEL__ */