2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QUICC Engine (QE) external definitions and structure.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #ifndef _ASM_POWERPC_QE_H
16 #define _ASM_POWERPC_QE_H
19 #include <asm/immap_qe.h>
21 #define QE_NUM_OF_SNUM 28
22 #define QE_NUM_OF_BRGS 16
23 #define QE_NUM_OF_PORTS 1024
27 #define MEM_PART_SYSTEM 0
28 #define MEM_PART_SECONDARY 1
29 #define MEM_PART_MURAM 2
31 /* Export QE common operations */
32 extern void qe_reset(void);
33 extern int par_io_init(struct device_node *np);
34 extern int par_io_of_config(struct device_node *np);
35 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
36 int assignment, int has_irq);
37 extern int par_io_data_set(u8 port, u8 pin, u8 val);
40 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
41 void qe_setbrg(u32 brg, u32 rate);
42 int qe_get_snum(void);
43 void qe_put_snum(u8 snum);
44 unsigned long qe_muram_alloc(int size, int align);
45 int qe_muram_free(unsigned long offset);
46 unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
47 void qe_muram_dump(void);
48 void *qe_muram_addr(unsigned long offset);
50 /* Buffer descriptors */
55 } __attribute__ ((packed));
57 #define BD_STATUS_MASK 0xffff0000
58 #define BD_LENGTH_MASK 0x0000ffff
61 #define QE_INTR_TABLE_ALIGN 16 /* ??? */
62 #define QE_ALIGNMENT_OF_BD 8
63 #define QE_ALIGNMENT_OF_PRAM 64
66 enum qe_risc_allocation {
67 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
68 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
69 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
73 /* QE extended filtering Table Lookup Key Size */
74 enum qe_fltr_tbl_lookup_key_size {
75 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
76 = 0x3f, /* LookupKey parsed by the Generate LookupKey
77 CMD is truncated to 8 bytes */
78 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
79 = 0x5f, /* LookupKey parsed by the Generate LookupKey
80 CMD is truncated to 16 bytes */
83 /* QE FLTR extended filtering Largest External Table Lookup Key Size */
84 enum qe_fltr_largest_external_tbl_lookup_key_size {
85 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
87 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
88 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
89 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
90 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
93 /* structure representing QE parameter RAM */
94 struct qe_timer_tables {
95 u16 tm_base; /* QE timer table base adr */
96 u16 tm_ptr; /* QE timer table pointer */
97 u16 r_tmr; /* QE timer mode register */
98 u16 r_tmv; /* QE timer valid register */
99 u32 tm_cmd; /* QE timer cmd register */
100 u32 tm_cnt; /* QE timer internal cnt */
101 } __attribute__ ((packed));
103 #define QE_FLTR_TAD_SIZE 8
105 /* QE extended filtering Termination Action Descriptor (TAD) */
107 u8 serialized[QE_FLTR_TAD_SIZE];
108 } __attribute__ ((packed));
110 /* Communication Direction */
115 COMM_DIR_RX_AND_TX = 3
118 /* Clocks and BRGs */
121 QE_BRG1, /* Baud Rate Generator 1 */
122 QE_BRG2, /* Baud Rate Generator 2 */
123 QE_BRG3, /* Baud Rate Generator 3 */
124 QE_BRG4, /* Baud Rate Generator 4 */
125 QE_BRG5, /* Baud Rate Generator 5 */
126 QE_BRG6, /* Baud Rate Generator 6 */
127 QE_BRG7, /* Baud Rate Generator 7 */
128 QE_BRG8, /* Baud Rate Generator 8 */
129 QE_BRG9, /* Baud Rate Generator 9 */
130 QE_BRG10, /* Baud Rate Generator 10 */
131 QE_BRG11, /* Baud Rate Generator 11 */
132 QE_BRG12, /* Baud Rate Generator 12 */
133 QE_BRG13, /* Baud Rate Generator 13 */
134 QE_BRG14, /* Baud Rate Generator 14 */
135 QE_BRG15, /* Baud Rate Generator 15 */
136 QE_BRG16, /* Baud Rate Generator 16 */
137 QE_CLK1, /* Clock 1 */
138 QE_CLK2, /* Clock 2 */
139 QE_CLK3, /* Clock 3 */
140 QE_CLK4, /* Clock 4 */
141 QE_CLK5, /* Clock 5 */
142 QE_CLK6, /* Clock 6 */
143 QE_CLK7, /* Clock 7 */
144 QE_CLK8, /* Clock 8 */
145 QE_CLK9, /* Clock 9 */
146 QE_CLK10, /* Clock 10 */
147 QE_CLK11, /* Clock 11 */
148 QE_CLK12, /* Clock 12 */
149 QE_CLK13, /* Clock 13 */
150 QE_CLK14, /* Clock 14 */
151 QE_CLK15, /* Clock 15 */
152 QE_CLK16, /* Clock 16 */
153 QE_CLK17, /* Clock 17 */
154 QE_CLK18, /* Clock 18 */
155 QE_CLK19, /* Clock 19 */
156 QE_CLK20, /* Clock 20 */
157 QE_CLK21, /* Clock 21 */
158 QE_CLK22, /* Clock 22 */
159 QE_CLK23, /* Clock 23 */
160 QE_CLK24, /* Clock 24 */
164 /* QE CMXUCR Registers.
165 * There are two UCCs represented in each of the four CMXUCR registers.
166 * These values are for the UCC in the LSBs
168 #define QE_CMXUCR_MII_ENET_MNG 0x00007000
169 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
170 #define QE_CMXUCR_GRANT 0x00008000
171 #define QE_CMXUCR_TSA 0x00004000
172 #define QE_CMXUCR_BKPT 0x00000100
173 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
175 /* QE CMXGCR Registers.
177 #define QE_CMXGCR_MII_ENET_MNG 0x00007000
178 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
179 #define QE_CMXGCR_USBCS 0x0000000f
183 #define QE_CR_FLG 0x00010000
184 #define QE_RESET 0x80000000
185 #define QE_INIT_TX_RX 0x00000000
186 #define QE_INIT_RX 0x00000001
187 #define QE_INIT_TX 0x00000002
188 #define QE_ENTER_HUNT_MODE 0x00000003
189 #define QE_STOP_TX 0x00000004
190 #define QE_GRACEFUL_STOP_TX 0x00000005
191 #define QE_RESTART_TX 0x00000006
192 #define QE_CLOSE_RX_BD 0x00000007
193 #define QE_SWITCH_COMMAND 0x00000007
194 #define QE_SET_GROUP_ADDRESS 0x00000008
195 #define QE_START_IDMA 0x00000009
196 #define QE_MCC_STOP_RX 0x00000009
197 #define QE_ATM_TRANSMIT 0x0000000a
198 #define QE_HPAC_CLEAR_ALL 0x0000000b
199 #define QE_GRACEFUL_STOP_RX 0x0000001a
200 #define QE_RESTART_RX 0x0000001b
201 #define QE_HPAC_SET_PRIORITY 0x0000010b
202 #define QE_HPAC_STOP_TX 0x0000020b
203 #define QE_HPAC_STOP_RX 0x0000030b
204 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
205 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
206 #define QE_HPAC_START_TX 0x0000060b
207 #define QE_HPAC_START_RX 0x0000070b
208 #define QE_USB_STOP_TX 0x0000000a
209 #define QE_USB_RESTART_TX 0x0000000b
210 #define QE_QMC_STOP_TX 0x0000000c
211 #define QE_QMC_STOP_RX 0x0000000d
212 #define QE_SS7_SU_FIL_RESET 0x0000000e
213 /* jonathbr added from here down for 83xx */
214 #define QE_RESET_BCS 0x0000000a
215 #define QE_MCC_INIT_TX_RX_16 0x00000003
216 #define QE_MCC_STOP_TX 0x00000004
217 #define QE_MCC_INIT_TX_1 0x00000005
218 #define QE_MCC_INIT_RX_1 0x00000006
219 #define QE_MCC_RESET 0x00000007
220 #define QE_SET_TIMER 0x00000008
221 #define QE_RANDOM_NUMBER 0x0000000c
222 #define QE_ATM_MULTI_THREAD_INIT 0x00000011
223 #define QE_ASSIGN_PAGE 0x00000012
224 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
225 #define QE_START_FLOW_CONTROL 0x00000014
226 #define QE_STOP_FLOW_CONTROL 0x00000015
227 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
229 #define QE_ASSIGN_RISC 0x00000010
230 #define QE_CR_MCN_NORMAL_SHIFT 6
231 #define QE_CR_MCN_USB_SHIFT 4
232 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
233 #define QE_CR_SNUM_SHIFT 17
235 /* QE CECR Sub Block - sub block of QE command.
237 #define QE_CR_SUBBLOCK_INVALID 0x00000000
238 #define QE_CR_SUBBLOCK_USB 0x03200000
239 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
240 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
241 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
242 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
243 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
244 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
245 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
246 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
247 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
248 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
249 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
250 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
251 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
252 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
253 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
254 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
255 #define QE_CR_SUBBLOCK_MCC1 0x03800000
256 #define QE_CR_SUBBLOCK_MCC2 0x03a00000
257 #define QE_CR_SUBBLOCK_MCC3 0x03000000
258 #define QE_CR_SUBBLOCK_IDMA1 0x02800000
259 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
260 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
261 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
262 #define QE_CR_SUBBLOCK_HPAC 0x01e00000
263 #define QE_CR_SUBBLOCK_SPI1 0x01400000
264 #define QE_CR_SUBBLOCK_SPI2 0x01600000
265 #define QE_CR_SUBBLOCK_RAND 0x01c00000
266 #define QE_CR_SUBBLOCK_TIMER 0x01e00000
267 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
269 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
270 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
271 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
272 #define QE_CR_PROTOCOL_ATM_POS 0x0A
273 #define QE_CR_PROTOCOL_ETHERNET 0x0C
274 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
277 #define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */
278 #define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */
279 #define QE_BMR_BYTE_ORDER_BO_MAX 0x18
281 /* BRG configuration register */
282 #define QE_BRGC_ENABLE 0x00010000
283 #define QE_BRGC_DIVISOR_SHIFT 1
284 #define QE_BRGC_DIVISOR_MAX 0xFFF
285 #define QE_BRGC_DIV16 1
287 /* QE Timers registers */
288 #define QE_GTCFR1_PCAS 0x80
289 #define QE_GTCFR1_STP2 0x20
290 #define QE_GTCFR1_RST2 0x10
291 #define QE_GTCFR1_GM2 0x08
292 #define QE_GTCFR1_GM1 0x04
293 #define QE_GTCFR1_STP1 0x02
294 #define QE_GTCFR1_RST1 0x01
297 #define QE_SDSR_BER1 0x02000000
298 #define QE_SDSR_BER2 0x01000000
300 #define QE_SDMR_GLB_1_MSK 0x80000000
301 #define QE_SDMR_ADR_SEL 0x20000000
302 #define QE_SDMR_BER1_MSK 0x02000000
303 #define QE_SDMR_BER2_MSK 0x01000000
304 #define QE_SDMR_EB1_MSK 0x00800000
305 #define QE_SDMR_ER1_MSK 0x00080000
306 #define QE_SDMR_ER2_MSK 0x00040000
307 #define QE_SDMR_CEN_MASK 0x0000E000
308 #define QE_SDMR_SBER_1 0x00000200
309 #define QE_SDMR_SBER_2 0x00000200
310 #define QE_SDMR_EB1_PR_MASK 0x000000C0
311 #define QE_SDMR_ER1_PR 0x00000008
313 #define QE_SDMR_CEN_SHIFT 13
314 #define QE_SDMR_EB1_PR_SHIFT 6
316 #define QE_SDTM_MSNUM_SHIFT 24
318 #define QE_SDEBCR_BA_MASK 0x01FFFFFF
321 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
322 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
323 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
324 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
325 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
328 #define UCC_GUEMR_MODE_MASK_RX 0x02
329 #define UCC_GUEMR_MODE_MASK_TX 0x01
330 #define UCC_GUEMR_MODE_FAST_RX 0x02
331 #define UCC_GUEMR_MODE_FAST_TX 0x01
332 #define UCC_GUEMR_MODE_SLOW_RX 0x00
333 #define UCC_GUEMR_MODE_SLOW_TX 0x00
334 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
337 /* structure representing UCC SLOW parameter RAM */
338 struct ucc_slow_pram {
339 u16 rbase; /* RX BD base address */
340 u16 tbase; /* TX BD base address */
341 u8 rfcr; /* Rx function code */
342 u8 tfcr; /* Tx function code */
343 u16 mrblr; /* Rx buffer length */
344 u32 rstate; /* Rx internal state */
345 u32 rptr; /* Rx internal data pointer */
346 u16 rbptr; /* rb BD Pointer */
347 u16 rcount; /* Rx internal byte count */
348 u32 rtemp; /* Rx temp */
349 u32 tstate; /* Tx internal state */
350 u32 tptr; /* Tx internal data pointer */
351 u16 tbptr; /* Tx BD pointer */
352 u16 tcount; /* Tx byte count */
353 u32 ttemp; /* Tx temp */
354 u32 rcrc; /* temp receive CRC */
355 u32 tcrc; /* temp transmit CRC */
356 } __attribute__ ((packed));
358 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
359 #define UCC_SLOW_GUMR_H_CRC16 0x00004000
360 #define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000
361 #define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000
362 #define UCC_SLOW_GUMR_H_REVD 0x00002000
363 #define UCC_SLOW_GUMR_H_TRX 0x00001000
364 #define UCC_SLOW_GUMR_H_TTX 0x00000800
365 #define UCC_SLOW_GUMR_H_CDP 0x00000400
366 #define UCC_SLOW_GUMR_H_CTSP 0x00000200
367 #define UCC_SLOW_GUMR_H_CDS 0x00000100
368 #define UCC_SLOW_GUMR_H_CTSS 0x00000080
369 #define UCC_SLOW_GUMR_H_TFL 0x00000040
370 #define UCC_SLOW_GUMR_H_RFW 0x00000020
371 #define UCC_SLOW_GUMR_H_TXSY 0x00000010
372 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004
373 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008
374 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
375 #define UCC_SLOW_GUMR_H_RTSM 0x00000002
376 #define UCC_SLOW_GUMR_H_RSYN 0x00000001
378 #define UCC_SLOW_GUMR_L_TCI 0x10000000
379 #define UCC_SLOW_GUMR_L_RINV 0x02000000
380 #define UCC_SLOW_GUMR_L_TINV 0x01000000
381 #define UCC_SLOW_GUMR_L_TEND 0x00020000
382 #define UCC_SLOW_GUMR_L_ENR 0x00000020
383 #define UCC_SLOW_GUMR_L_ENT 0x00000010
385 /* General UCC FAST Mode Register */
386 #define UCC_FAST_GUMR_TCI 0x20000000
387 #define UCC_FAST_GUMR_TRX 0x10000000
388 #define UCC_FAST_GUMR_TTX 0x08000000
389 #define UCC_FAST_GUMR_CDP 0x04000000
390 #define UCC_FAST_GUMR_CTSP 0x02000000
391 #define UCC_FAST_GUMR_CDS 0x01000000
392 #define UCC_FAST_GUMR_CTSS 0x00800000
393 #define UCC_FAST_GUMR_TXSY 0x00020000
394 #define UCC_FAST_GUMR_RSYN 0x00010000
395 #define UCC_FAST_GUMR_RTSM 0x00002000
396 #define UCC_FAST_GUMR_REVD 0x00000400
397 #define UCC_FAST_GUMR_ENR 0x00000020
398 #define UCC_FAST_GUMR_ENT 0x00000010
400 /* Slow UCC Event Register (UCCE) */
401 #define UCC_SLOW_UCCE_GLR 0x1000
402 #define UCC_SLOW_UCCE_GLT 0x0800
403 #define UCC_SLOW_UCCE_DCC 0x0400
404 #define UCC_SLOW_UCCE_FLG 0x0200
405 #define UCC_SLOW_UCCE_AB 0x0200
406 #define UCC_SLOW_UCCE_IDLE 0x0100
407 #define UCC_SLOW_UCCE_GRA 0x0080
408 #define UCC_SLOW_UCCE_TXE 0x0010
409 #define UCC_SLOW_UCCE_RXF 0x0008
410 #define UCC_SLOW_UCCE_CCR 0x0008
411 #define UCC_SLOW_UCCE_RCH 0x0008
412 #define UCC_SLOW_UCCE_BSY 0x0004
413 #define UCC_SLOW_UCCE_TXB 0x0002
414 #define UCC_SLOW_UCCE_TX 0x0002
415 #define UCC_SLOW_UCCE_RX 0x0001
416 #define UCC_SLOW_UCCE_GOV 0x0001
417 #define UCC_SLOW_UCCE_GUN 0x0002
418 #define UCC_SLOW_UCCE_GINT 0x0004
419 #define UCC_SLOW_UCCE_IQOV 0x0008
421 #define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
422 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF | \
423 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
424 #define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
425 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF)
426 #define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
427 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
428 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
429 #define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY | UCC_SLOW_UCCE_GRA | \
430 UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \
431 UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR)
432 #define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV | UCC_SLOW_UCCE_GINT | \
433 UCC_SLOW_UCCE_GUN | UCC_SLOW_UCCE_GOV)
435 #define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \
436 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | \
439 #define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB
440 #define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX)
441 #define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX)
443 /* UCC Transmit On Demand Register (UTODR) */
444 #define UCC_SLOW_TOD 0x8000
445 #define UCC_FAST_TOD 0x8000
447 /* Function code masks */
449 #define FC_DTB_LCL 0x02
450 #define UCC_FAST_FUNCTION_CODE_GBL 0x20
451 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
452 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
454 #endif /* __KERNEL__ */
455 #endif /* _ASM_POWERPC_QE_H */