1 #ifndef _ASM_POWERPC_PGTABLE_PPC32_H
2 #define _ASM_POWERPC_PGTABLE_PPC32_H
4 #include <asm-generic/4level-fixup.h>
7 #include <linux/sched.h>
8 #include <linux/threads.h>
9 #include <asm/processor.h> /* For TASK_SIZE */
12 #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
15 extern unsigned long va_to_phys(unsigned long address);
16 extern pte_t *va_to_pte(unsigned long address);
17 extern unsigned long ioremap_bot, ioremap_base;
18 #endif /* __ASSEMBLY__ */
21 * The PowerPC MMU uses a hash table containing PTEs, together with
22 * a set of 16 segment registers (on 32-bit implementations), to define
23 * the virtual to physical address mapping.
25 * We use the hash table as an extended TLB, i.e. a cache of currently
26 * active mappings. We maintain a two-level page table tree, much
27 * like that used by the i386, for the sake of the Linux memory
28 * management code. Low-level assembler code in hashtable.S
29 * (procedure hash_page) is responsible for extracting ptes from the
30 * tree and putting them into the hash table when necessary, and
31 * updating the accessed and modified bits in the page table tree.
35 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
36 * We also use the two level tables, but we can put the real bits in them
37 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
38 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
39 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
40 * based upon user/super access. The TLB does not have accessed nor write
41 * protect. We assume that if the TLB get loaded with an entry it is
42 * accessed, and overload the changed bit for write protect. We use
43 * two bits in the software pte that are supposed to be set to zero in
44 * the TLB entry (24 and 25) for these indicators. Although the level 1
45 * descriptor contains the guarded and writethrough/copyback bits, we can
46 * set these at the page level since they get copied from the Mx_TWC
47 * register when the TLB entry is loaded. We will use bit 27 for guard, since
48 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
49 * These will get masked from the level 2 descriptor at TLB load time, and
50 * copied to the MD_TWC before it gets loaded.
51 * Large page sizes added. We currently support two sizes, 4K and 8M.
52 * This also allows a TLB hander optimization because we can directly
53 * load the PMD into MD_TWC. The 8M pages are only used for kernel
54 * mapping of well known areas. The PMD (PGD) entries contain control
55 * flags in addition to the address, so care must be taken that the
56 * software no longer assumes these are only pointers.
60 * At present, all PowerPC 400-class processors share a similar TLB
61 * architecture. The instruction and data sides share a unified,
62 * 64-entry, fully-associative TLB which is maintained totally under
63 * software control. In addition, the instruction side has a
64 * hardware-managed, 4-entry, fully-associative TLB which serves as a
65 * first level to the shared TLB. These two TLBs are known as the UTLB
66 * and ITLB, respectively (see "mmu.h" for definitions).
70 * The normal case is that PTEs are 32-bits and we have a 1-page
71 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
73 * For any >32-bit physical address platform, we can use the following
74 * two level page table layout where the pgdir is 8KB and the MS 13 bits
75 * are an index to the second level table. The combined pgdir/pmd first
76 * level has 2048 entries and the second level has 512 64-bit PTE entries.
79 /* PMD_SHIFT determines the size of the area mapped by the PTE pages */
80 #define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT)
81 #define PMD_SIZE (1UL << PMD_SHIFT)
82 #define PMD_MASK (~(PMD_SIZE-1))
84 /* PGDIR_SHIFT determines what a top-level page table entry can map */
85 #define PGDIR_SHIFT PMD_SHIFT
86 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
87 #define PGDIR_MASK (~(PGDIR_SIZE-1))
90 * entries per page directory level: our page-table tree is two-level, so
91 * we don't really have any PMD directory.
93 #define PTRS_PER_PTE (1 << PTE_SHIFT)
94 #define PTRS_PER_PMD 1
95 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
97 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
98 #define FIRST_USER_ADDRESS 0
100 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
101 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
103 #define pte_ERROR(e) \
104 printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
105 (unsigned long long)pte_val(e))
106 #define pmd_ERROR(e) \
107 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
108 #define pgd_ERROR(e) \
109 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
112 * Just any arbitrary offset to the start of the vmalloc VM area: the
113 * current 64MB value just means that there will be a 64MB "hole" after the
114 * physical memory until the kernel virtual memory starts. That means that
115 * any out-of-bounds memory accesses will hopefully be caught.
116 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
117 * area for the same reason. ;)
119 * We no longer map larger than phys RAM with the BATs so we don't have
120 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
121 * about clashes between our early calls to ioremap() that start growing down
122 * from ioremap_base being run into the VM area allocations (growing upwards
123 * from VMALLOC_START). For this reason we have ioremap_bot to check when
124 * we actually run into our mappings setup in the early boot with the VM
125 * system. This really does become a problem for machines with good amounts
128 #define VMALLOC_OFFSET (0x1000000) /* 16M */
130 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
132 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
134 #define VMALLOC_END ioremap_bot
137 * Bits in a linux-style PTE. These match the bits in the
138 * (hardware-defined) PowerPC PTE as closely as possible.
141 #if defined(CONFIG_40x)
143 /* There are several potential gotchas here. The 40x hardware TLBLO
144 field looks like this:
146 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
147 RPN..................... 0 0 EX WR ZSEL....... W I M G
149 Where possible we make the Linux PTE bits match up with this
151 - bits 20 and 21 must be cleared, because we use 4k pages (40x can
152 support down to 1k pages), this is done in the TLBMiss exception
154 - We use only zones 0 (for kernel pages) and 1 (for user pages)
155 of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
156 miss handler. Bit 27 is PAGE_USER, thus selecting the correct
158 - PRESENT *must* be in the bottom two bits because swap cache
159 entries use the top 30 bits. Because 40x doesn't support SMP
160 anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
161 is cleared in the TLB miss handler before the TLB entry is loaded.
162 - All other bits of the PTE are loaded into TLBLO without
163 modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
164 software PTE bits. We actually use use bits 21, 24, 25, and
165 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
169 /* Definitions for 40x embedded chips. */
170 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
171 #define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
172 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
173 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
174 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
175 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
176 #define _PAGE_RW 0x040 /* software: Writes permitted */
177 #define _PAGE_DIRTY 0x080 /* software: dirty page */
178 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
179 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
180 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
182 #define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
183 #define _PMD_BAD 0x802
184 #define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
185 #define _PMD_SIZE_4M 0x0c0
186 #define _PMD_SIZE_16M 0x0e0
187 #define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
189 #elif defined(CONFIG_44x)
191 * Definitions for PPC440
193 * Because of the 3 word TLB entries to support 36-bit addressing,
194 * the attribute are difficult to map in such a fashion that they
195 * are easily loaded during exception processing. I decided to
196 * organize the entry so the ERPN is the only portion in the
197 * upper word of the PTE and the attribute bits below are packed
198 * in as sensibly as they can be in the area below a 4KB page size
199 * oriented RPN. This at least makes it easy to load the RPN and
200 * ERPN fields in the TLB. -Matt
202 * Note that these bits preclude future use of a page size
206 * PPC 440 core has following TLB attribute fields;
209 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
210 * RPN................................. - - - - - - ERPN.......
213 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
214 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
216 * There are some constrains and options, to decide mapping software bits
219 * - PRESENT *must* be in the bottom three bits because swap cache
220 * entries use the top 29 bits for TLB2.
222 * - FILE *must* be in the bottom three bits because swap cache
223 * entries use the top 29 bits for TLB2.
225 * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
226 * doesn't support SMP. So we can use this as software bit, like
229 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
230 * for memory protection related functions (see PTE structure in
231 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
232 * above bits. Note that the bit values are CPU specific, not architecture
235 * The kernel PTE entry holds an arch-dependent swp_entry structure under
236 * certain situations. In other words, in such situations some portion of
237 * the PTE bits are used as a swp_entry. In the PPC implementation, the
238 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
239 * hold protection values. That means the three protection bits are
240 * reserved for both PTE and SWAP entry at the most significant three
243 * There are three protection bits available for SWAP entry:
246 * _PAGE_HASHPTE (if HW has)
248 * So those three bits have to be inside of 0-2nd LSB of PTE.
252 #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
253 #define _PAGE_RW 0x00000002 /* S: Write permission */
254 #define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
255 #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
256 #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */
257 #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */
258 #define _PAGE_USER 0x00000040 /* S: User page */
259 #define _PAGE_ENDIAN 0x00000080 /* H: E bit */
260 #define _PAGE_GUARDED 0x00000100 /* H: G bit */
261 #define _PAGE_DIRTY 0x00000200 /* S: Page dirty */
262 #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
263 #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
265 /* TODO: Add large page lowmem mapping support */
266 #define _PMD_PRESENT 0
267 #define _PMD_PRESENT_MASK (PAGE_MASK)
268 #define _PMD_BAD (~PAGE_MASK)
270 /* ERPN in a PTE never gets cleared, ignore it */
271 #define _PTE_NONE_MASK 0xffffffff00000000ULL
273 #elif defined(CONFIG_FSL_BOOKE)
275 MMU Assist Register 3:
277 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
278 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
280 - PRESENT *must* be in the bottom three bits because swap cache
281 entries use the top 29 bits.
283 - FILE *must* be in the bottom three bits because swap cache
284 entries use the top 29 bits.
287 /* Definitions for FSL Book-E Cores */
288 #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
289 #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
290 #define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
291 #define _PAGE_ACCESSED 0x00004 /* S: Page referenced */
292 #define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */
293 #define _PAGE_RW 0x00010 /* S: Write permission */
294 #define _PAGE_HWEXEC 0x00020 /* H: UX permission */
296 #define _PAGE_ENDIAN 0x00040 /* H: E bit */
297 #define _PAGE_GUARDED 0x00080 /* H: G bit */
298 #define _PAGE_COHERENT 0x00100 /* H: M bit */
299 #define _PAGE_NO_CACHE 0x00200 /* H: I bit */
300 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
302 #ifdef CONFIG_PTE_64BIT
303 #define _PAGE_DIRTY 0x08000 /* S: Page dirty */
305 /* ERPN in a PTE never gets cleared, ignore it */
306 #define _PTE_NONE_MASK 0xffffffffffff0000ULL
308 #define _PAGE_DIRTY 0x00800 /* S: Page dirty */
311 #define _PMD_PRESENT 0
312 #define _PMD_PRESENT_MASK (PAGE_MASK)
313 #define _PMD_BAD (~PAGE_MASK)
315 #elif defined(CONFIG_8xx)
316 /* Definitions for 8xx embedded chips. */
317 #define _PAGE_PRESENT 0x0001 /* Page is valid */
318 #define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
319 #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
320 #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
322 /* These five software bits must be masked out when the entry is loaded
325 #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
326 #define _PAGE_GUARDED 0x0010 /* software: guarded access */
327 #define _PAGE_DIRTY 0x0020 /* software: page changed */
328 #define _PAGE_RW 0x0040 /* software: user write access allowed */
329 #define _PAGE_ACCESSED 0x0080 /* software: page referenced */
331 /* Setting any bits in the nibble with the follow two controls will
332 * require a TLB exception handler change. It is assumed unused bits
335 #define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
336 #define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
338 #define _PMD_PRESENT 0x0001
339 #define _PMD_BAD 0x0ff0
340 #define _PMD_PAGE_MASK 0x000c
341 #define _PMD_PAGE_8M 0x000c
344 * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
345 * for an address even if _PAGE_PRESENT is not set, as a performance
346 * optimization. This is a bug if you ever want to use swap unless
347 * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
348 * definitions for __swp_entry etc. below, which would be gross.
351 #define _PTE_NONE_MASK _PAGE_ACCESSED
353 #else /* CONFIG_6xx */
354 /* Definitions for 60x, 740/750, etc. */
355 #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
356 #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
357 #define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */
358 #define _PAGE_USER 0x004 /* usermode access allowed */
359 #define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
360 #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
361 #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
362 #define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
363 #define _PAGE_DIRTY 0x080 /* C: page changed */
364 #define _PAGE_ACCESSED 0x100 /* R: page referenced */
365 #define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
366 #define _PAGE_RW 0x400 /* software: user write access allowed */
368 #define _PTE_NONE_MASK _PAGE_HASHPTE
370 #define _PMD_PRESENT 0
371 #define _PMD_PRESENT_MASK (PAGE_MASK)
372 #define _PMD_BAD (~PAGE_MASK)
376 * Some bits are only used on some cpu families...
378 #ifndef _PAGE_HASHPTE
379 #define _PAGE_HASHPTE 0
381 #ifndef _PTE_NONE_MASK
382 #define _PTE_NONE_MASK 0
385 #define _PAGE_SHARED 0
387 #ifndef _PAGE_HWWRITE
388 #define _PAGE_HWWRITE 0
391 #define _PAGE_HWEXEC 0
396 #ifndef _PMD_PRESENT_MASK
397 #define _PMD_PRESENT_MASK _PMD_PRESENT
401 #define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
404 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
407 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
408 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
409 * to have it in the Linux PTE, and in fact the bit could be reused for
410 * another purpose. -- paulus.
414 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
416 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
418 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
419 #define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
421 #ifdef CONFIG_PPC_STD_MMU
422 /* On standard PPC MMU, no user access implies kernel read/write access,
423 * so to write-protect kernel memory we must turn on user access */
424 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
426 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
429 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
430 #define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC)
432 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
433 /* We want the debuggers to be able to set breakpoints anywhere, so
434 * don't write protect the kernel text */
435 #define _PAGE_RAM_TEXT _PAGE_RAM
437 #define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
440 #define PAGE_NONE __pgprot(_PAGE_BASE)
441 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
442 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
443 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
444 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
445 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
446 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
448 #define PAGE_KERNEL __pgprot(_PAGE_RAM)
449 #define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO)
452 * The PowerPC can only do execute protection on a segment (256MB) basis,
453 * not on a page basis. So we consider execute permission the same as read.
454 * Also, write permissions imply read permissions.
455 * This is the closest we can get..
457 #define __P000 PAGE_NONE
458 #define __P001 PAGE_READONLY_X
459 #define __P010 PAGE_COPY
460 #define __P011 PAGE_COPY_X
461 #define __P100 PAGE_READONLY
462 #define __P101 PAGE_READONLY_X
463 #define __P110 PAGE_COPY
464 #define __P111 PAGE_COPY_X
466 #define __S000 PAGE_NONE
467 #define __S001 PAGE_READONLY_X
468 #define __S010 PAGE_SHARED
469 #define __S011 PAGE_SHARED_X
470 #define __S100 PAGE_READONLY
471 #define __S101 PAGE_READONLY_X
472 #define __S110 PAGE_SHARED
473 #define __S111 PAGE_SHARED_X
476 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
477 * kernel without large page PMD support */
478 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
481 * Conversions between PTE values and page frame numbers.
484 /* in some case we want to additionaly adjust where the pfn is in the pte to
485 * allow room for more flags */
486 #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
487 #define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
489 #define PFN_SHIFT_OFFSET (PAGE_SHIFT)
492 #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
493 #define pte_page(x) pfn_to_page(pte_pfn(x))
495 #define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
497 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
500 * ZERO_PAGE is a global shared page that is always zero: used
501 * for zero-mapped memory areas etc..
503 extern unsigned long empty_zero_page[1024];
504 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
506 #endif /* __ASSEMBLY__ */
508 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
509 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
510 #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
512 #define pmd_none(pmd) (!pmd_val(pmd))
513 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
514 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
515 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
519 * The "pgd_xxx()" functions here are trivial for a folded two-level
520 * setup: the pgd is never bad, and a pmd always exists (as it's folded
521 * into the pgd entry)
523 static inline int pgd_none(pgd_t pgd) { return 0; }
524 static inline int pgd_bad(pgd_t pgd) { return 0; }
525 static inline int pgd_present(pgd_t pgd) { return 1; }
526 #define pgd_clear(xp) do { } while (0)
528 #define pgd_page_vaddr(pgd) \
529 ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
532 * The following only work if pte_present() is true.
533 * Undefined behaviour if not..
535 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
536 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
537 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
538 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
539 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
540 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
542 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
543 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
545 static inline pte_t pte_rdprotect(pte_t pte) {
546 pte_val(pte) &= ~_PAGE_USER; return pte; }
547 static inline pte_t pte_wrprotect(pte_t pte) {
548 pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
549 static inline pte_t pte_exprotect(pte_t pte) {
550 pte_val(pte) &= ~_PAGE_EXEC; return pte; }
551 static inline pte_t pte_mkclean(pte_t pte) {
552 pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
553 static inline pte_t pte_mkold(pte_t pte) {
554 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
556 static inline pte_t pte_mkread(pte_t pte) {
557 pte_val(pte) |= _PAGE_USER; return pte; }
558 static inline pte_t pte_mkexec(pte_t pte) {
559 pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
560 static inline pte_t pte_mkwrite(pte_t pte) {
561 pte_val(pte) |= _PAGE_RW; return pte; }
562 static inline pte_t pte_mkdirty(pte_t pte) {
563 pte_val(pte) |= _PAGE_DIRTY; return pte; }
564 static inline pte_t pte_mkyoung(pte_t pte) {
565 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
567 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
569 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
574 * When flushing the tlb entry for a page, we also need to flush the hash
575 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
577 extern int flush_hash_pages(unsigned context, unsigned long va,
578 unsigned long pmdval, int count);
580 /* Add an HPTE to the hash table */
581 extern void add_hash_page(unsigned context, unsigned long va,
582 unsigned long pmdval);
585 * Atomic PTE updates.
587 * pte_update clears and sets bit atomically, and returns
588 * the old pte value. In the 64-bit PTE case we lock around the
589 * low PTE word since we expect ALL flag bits to be there
591 #ifndef CONFIG_PTE_64BIT
592 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
595 unsigned long old, tmp;
597 __asm__ __volatile__("\
604 : "=&r" (old), "=&r" (tmp), "=m" (*p)
605 : "r" (p), "r" (clr), "r" (set), "m" (*p)
610 static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
613 unsigned long long old;
616 __asm__ __volatile__("\
624 : "=&r" (old), "=&r" (tmp), "=m" (*p)
625 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
632 * set_pte stores a linux PTE into the linux page table.
633 * On machines which use an MMU hash table we avoid changing the
636 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
637 pte_t *ptep, pte_t pte)
639 #if _PAGE_HASHPTE != 0
640 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
647 * 2.6 calles this without flushing the TLB entry, this is wrong
648 * for our hash-based implementation, we fix that up here
650 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
651 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
654 old = pte_update(ptep, _PAGE_ACCESSED, 0);
655 #if _PAGE_HASHPTE != 0
656 if (old & _PAGE_HASHPTE) {
657 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
658 flush_hash_pages(context, addr, ptephys, 1);
661 return (old & _PAGE_ACCESSED) != 0;
663 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
664 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
666 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
667 static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma,
668 unsigned long addr, pte_t *ptep)
670 return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
673 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
674 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
677 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
680 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
681 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
684 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
687 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
688 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
690 unsigned long bits = pte_val(entry) &
691 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
692 pte_update(ptep, 0, bits);
695 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
697 __ptep_set_access_flags(__ptep, __entry, __dirty); \
698 flush_tlb_page_nohash(__vma, __address); \
702 * Macro to mark a page protection value as "uncacheable".
704 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
707 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
708 unsigned long size, pgprot_t vma_prot);
709 #define __HAVE_PHYS_MEM_ACCESS_PROT
711 #define __HAVE_ARCH_PTE_SAME
712 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
715 * Note that on Book E processors, the pmd contains the kernel virtual
716 * (lowmem) address of the pte page. The physical address is less useful
717 * because everything runs with translation enabled (even the TLB miss
718 * handler). On everything else the pmd contains the physical address
719 * of the pte page. -- paulus
722 #define pmd_page_vaddr(pmd) \
723 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
724 #define pmd_page(pmd) \
725 (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
727 #define pmd_page_vaddr(pmd) \
728 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
729 #define pmd_page(pmd) \
730 (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
733 /* to find an entry in a kernel page-table-directory */
734 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
736 /* to find an entry in a page-table-directory */
737 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
738 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
740 /* Find an entry in the second-level page table.. */
741 static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
743 return (pmd_t *) dir;
746 /* Find an entry in the third-level page table.. */
747 #define pte_index(address) \
748 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
749 #define pte_offset_kernel(dir, addr) \
750 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
751 #define pte_offset_map(dir, addr) \
752 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
753 #define pte_offset_map_nested(dir, addr) \
754 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
756 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
757 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
759 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
761 extern void paging_init(void);
764 * Encode and decode a swap entry.
765 * Note that the bits we use in a PTE for representing a swap entry
766 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
767 *_PAGE_HASHPTE bit (if used). -- paulus
769 #define __swp_type(entry) ((entry).val & 0x1f)
770 #define __swp_offset(entry) ((entry).val >> 5)
771 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
772 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
773 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
775 /* Encode and decode a nonlinear file mapping entry */
776 #define PTE_FILE_MAX_BITS 29
777 #define pte_to_pgoff(pte) (pte_val(pte) >> 3)
778 #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE })
781 /* For virtual address to physical address conversion */
782 extern void cache_clear(__u32 addr, int length);
783 extern void cache_push(__u32 addr, int length);
784 extern int mm_end_of_chunk (unsigned long addr, int len);
785 extern unsigned long iopa(unsigned long addr);
786 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
788 /* Values for nocacheflag and cmode */
789 /* These are not used by the APUS kernel_map, but prevents
790 compilation errors. */
791 #define KERNELMAP_FULL_CACHING 0
792 #define KERNELMAP_NOCACHE_SER 1
793 #define KERNELMAP_NOCACHE_NONSER 2
794 #define KERNELMAP_NO_COPYBACK 3
797 * Map some physical address range into the kernel address space.
799 extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
800 int nocacheflag, unsigned long *memavailp );
803 * Set cache mode of (kernel space) address range.
805 extern void kernel_set_cachemode (unsigned long address, unsigned long size,
808 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
809 #define kern_addr_valid(addr) (1)
811 #ifdef CONFIG_PHYS_64BIT
812 extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
813 unsigned long paddr, unsigned long size, pgprot_t prot);
815 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
821 phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
822 return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
825 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
826 remap_pfn_range(vma, vaddr, pfn, size, prot)
830 * No page table caches to initialise
832 #define pgtable_cache_init() do { } while (0)
834 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
837 #endif /* !__ASSEMBLY__ */
839 #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */