1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
6 #include <linux/ioport.h>
10 struct pci_controller;
13 * Structure of a PCI controller (host bridge)
15 struct pci_controller {
18 struct pci_controller *next;
19 struct device *parent;
25 void __iomem *io_base_virt;
26 resource_size_t io_base_phys;
28 /* Some machines (PReP) have a non 1:1 mapping of
29 * the PCI memory space in the CPU bus space
31 resource_size_t pci_mem_offset;
34 volatile unsigned int __iomem *cfg_addr;
35 volatile void __iomem *cfg_data;
38 * Used for variants of PCI indirect handling and possible quirks:
39 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
40 * EXT_REG - provides access to PCI-e extended registers
41 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
42 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
43 * to determine which bus number to match on when generating type0
46 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
47 #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
48 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
51 /* Currently, we limit ourselves to 1 IO range and 3 mem
52 * ranges since the common pci_bus structure can't handle more
54 struct resource io_resource;
55 struct resource mem_resources[3];
56 int global_number; /* PCI domain number */
59 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
64 /* These are used for config access before all the PCI probing
66 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
68 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
70 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
72 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
74 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
76 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
79 extern void setup_indirect_pci_nomap(struct pci_controller* hose,
80 void __iomem *cfg_addr, void __iomem *cfg_data);
81 extern void setup_indirect_pci(struct pci_controller* hose,
82 u32 cfg_addr, u32 cfg_data);
83 extern void setup_grackle(struct pci_controller *hose);
87 #include <linux/pci.h>
88 #include <linux/list.h>
91 * This program is free software; you can redistribute it and/or
92 * modify it under the terms of the GNU General Public License
93 * as published by the Free Software Foundation; either version
94 * 2 of the License, or (at your option) any later version.
98 * Structure of a PCI controller (host bridge)
100 struct pci_controller {
105 struct list_head list_node;
106 struct device *parent;
111 void __iomem *io_base_virt;
113 resource_size_t io_base_phys;
115 /* Some machines have a non 1:1 mapping of
116 * the PCI memory space in the CPU bus space
118 resource_size_t pci_mem_offset;
119 unsigned long pci_io_size;
122 volatile unsigned int __iomem *cfg_addr;
123 volatile void __iomem *cfg_data;
125 /* Currently, we limit ourselves to 1 IO range and 3 mem
126 * ranges since the common pci_bus structure can't handle more
128 struct resource io_resource;
129 struct resource mem_resources[3];
132 unsigned long dma_window_base_cur;
133 unsigned long dma_window_size;
139 * PCI stuff, for nodes representing PCI devices, pointed to
140 * by device_node->data.
142 struct pci_controller;
146 int busno; /* pci bus number */
147 int bussubno; /* pci subordinate bus number */
148 int devfn; /* pci device and function number */
149 int class_code; /* pci device class */
151 struct pci_controller *phb; /* for pci devices */
152 struct iommu_table *iommu_table; /* for phb's or bridges */
153 struct pci_dev *pcidev; /* back-pointer to the pci device */
154 struct device_node *node; /* back-pointer to the device_node */
156 int pci_ext_config_space; /* for pci devices */
159 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
161 int eeh_pe_config_addr; /* new-style partition endpoint address */
162 int eeh_check_count; /* # times driver ignored error */
163 int eeh_freeze_count; /* # times this device froze up. */
164 int eeh_false_positives; /* # times this device reported #ff's */
165 u32 config_space[16]; /* saved PCI config space */
169 /* Get the pointer to a device_node's pci_dn */
170 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
172 struct device_node *fetch_dev_dn(struct pci_dev *dev);
174 /* Get a device_node from a pci_dev. This code must be fast except
175 * in the case where the sysdata is incorrect and needs to be fixed
176 * up (this will only happen once).
177 * In this case the sysdata will have been inherited from a PCI host
178 * bridge or a PCI-PCI bridge further up the tree, so it will point
179 * to a valid struct pci_dn, just not the one we want.
181 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
183 struct device_node *dn = dev->sysdata;
184 struct pci_dn *pdn = dn->data;
186 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
187 return dn; /* fast path. sysdata is good */
188 return fetch_dev_dn(dev);
191 static inline int pci_device_from_OF_node(struct device_node *np,
196 *bus = PCI_DN(np)->busno;
197 *devfn = PCI_DN(np)->devfn;
201 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
204 return pci_device_to_OF_node(bus->self);
206 return bus->sysdata; /* Must be root bus (PHB) */
209 /** Find the bus corresponding to the indicated device node */
210 struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
212 /** Remove all of the PCI devices under this bus */
213 void pcibios_remove_pci_devices(struct pci_bus *bus);
215 /** Discover new pci devices under this bus, and add them */
216 void pcibios_add_pci_devices(struct pci_bus * bus);
217 void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
219 extern int pcibios_remove_root_bus(struct pci_controller *phb);
221 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
223 struct device_node *busdn = bus->sysdata;
225 BUG_ON(busdn == NULL);
226 return PCI_DN(busdn)->phb;
229 extern void pcibios_free_controller(struct pci_controller *phb);
231 extern void isa_bridge_find_early(struct pci_controller *hose);
233 extern int pcibios_unmap_io_space(struct pci_bus *bus);
234 extern int pcibios_map_io_space(struct pci_bus *bus);
236 /* Return values for ppc_md.pci_probe_mode function */
237 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
238 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
239 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
242 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
244 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
247 #endif /* CONFIG_PPC64 */
249 /* Get the PCI host controller for an OF device */
250 extern struct pci_controller*
251 pci_find_hose_for_OF_device(struct device_node* node);
253 /* Fill up host controller resources from the OF node */
255 pci_process_bridge_OF_ranges(struct pci_controller *hose,
256 struct device_node *dev, int primary);
258 /* Allocate a new PCI host bridge structure */
259 extern struct pci_controller *
260 pcibios_alloc_controller(struct device_node *dev);
262 extern unsigned long pci_address_to_pio(phys_addr_t address);
264 static inline unsigned long pci_address_to_pio(phys_addr_t address)
266 return (unsigned long)-1;
272 #endif /* __KERNEL__ */