2 * include/asm-powerpc/paca.h
4 * This control block defines the PACA which defines the processor
5 * specific data for each logical processor on the system.
6 * There are some pointers defined that are utilized by PLIC.
8 * C 2001 PPC 64 Team, IBM Corp
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 #ifndef _ASM_POWERPC_PACA_H
16 #define _ASM_POWERPC_PACA_H
18 #include <linux/config.h>
19 #include <asm/types.h>
20 #include <asm/lppaca.h>
23 register struct paca_struct *local_paca asm("r13");
24 #define get_paca() local_paca
29 * Defines the layout of the paca.
31 * This structure is not directly accessed by firmware or the service
32 * processor except for the first two pointers that point to the
33 * lppaca area and the ItLpRegSave area for this CPU. The lppaca
34 * object is currently contained within the PACA but it doesn't need
39 * Because hw_cpu_id, unlike other paca fields, is accessed
40 * routinely from other CPUs (from the IRQ code), we stick to
41 * read-only (after boot) fields in the first cacheline to
42 * avoid cacheline bouncing.
46 * MAGIC: These first two pointers can't be moved - they're
47 * accessed by the firmware
49 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
50 #ifdef CONFIG_PPC_ISERIES
51 void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
52 #endif /* CONFIG_PPC_ISERIES */
55 * MAGIC: the spinlock functions in arch/ppc64/lib/locks.c
56 * load lock_token and paca_index with a single lwz
57 * instruction. They must travel together and be properly
60 u16 lock_token; /* Constant 0x8000, used in locks */
61 u16 paca_index; /* Logical processor number */
63 u64 kernel_toc; /* Kernel TOC address */
64 u64 stab_real; /* Absolute address of segment table */
65 u64 stab_addr; /* Virtual address of segment table */
66 void *emergency_sp; /* pointer to emergency stack */
67 s16 hw_cpu_id; /* Physical processor number */
68 u8 cpu_start; /* At startup, processor spins until */
69 /* this becomes non-zero. */
72 * Now, starting in cacheline 2, the exception save areas
74 /* used for most interrupts/exceptions */
75 u64 exgen[10] __attribute__((aligned(0x80)));
76 u64 exmc[10]; /* used for machine checks */
77 u64 exslb[10]; /* used for SLB/segment table misses
78 * on the linear mapping */
79 #ifdef CONFIG_PPC_64K_PAGES
81 #endif /* CONFIG_PPC_64K_PAGES */
84 u16 slb_cache[SLB_CACHE_ENTRIES];
88 * then miscellaneous read-write fields
90 struct task_struct *__current; /* Pointer to current */
91 u64 kstack; /* Saved Kernel stack addr */
92 u64 stab_rr; /* stab/slb round-robin counter */
93 u64 saved_r1; /* r1 save for RTAS calls */
94 u64 saved_msr; /* MSR saved here by enter_rtas */
95 u8 proc_enabled; /* irq soft-enable flag */
98 * iSeries structure which the hypervisor knows about -
99 * this structure should not cross a page boundary.
100 * The vpa_init/register_vpa call is now known to fail if the
101 * lppaca structure crosses a page boundary.
102 * The lppaca is also used on POWER5 pSeries boxes.
103 * The lppaca is 640 bytes long, and cannot readily change
104 * since the hypervisor knows its layout, so a 1kB
105 * alignment will suffice to ensure that it doesn't
106 * cross a page boundary.
108 struct lppaca lppaca __attribute__((__aligned__(0x400)));
111 extern struct paca_struct paca[];
113 #endif /* _ASM_POWERPC_PACA_H */