1 #ifndef _ASM_POWERPC_MMU_H_
2 #define _ASM_POWERPC_MMU_H_
5 #include <asm-ppc/mmu.h>
9 * PowerPC memory management structures
11 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
20 #include <asm/asm-compat.h>
27 #define STE_ESID_V 0x80
28 #define STE_ESID_KS 0x20
29 #define STE_ESID_KP 0x10
30 #define STE_ESID_N 0x08
32 #define STE_VSID_SHIFT 12
34 /* Location of cpu0's segment table */
35 #define STAB0_PAGE 0x6
36 #define STAB0_OFFSET (STAB0_PAGE << 12)
37 #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
40 extern char initial_stab[];
41 #endif /* ! __ASSEMBLY */
47 #define SLB_NUM_BOLTED 3
48 #define SLB_CACHE_ENTRIES 8
50 /* Bits in the SLB ESID word */
51 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
53 /* Bits in the SLB VSID word */
54 #define SLB_VSID_SHIFT 12
55 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
56 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
57 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
58 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
59 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
60 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
61 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
62 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
63 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
64 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
65 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
66 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
67 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
68 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
70 #define SLB_VSID_KERNEL (SLB_VSID_KP)
71 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
73 #define SLBIE_C (0x08000000)
79 #define HPTES_PER_GROUP 8
81 #define HPTE_V_AVPN_SHIFT 7
82 #define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80)
83 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
84 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN))
85 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
86 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
87 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
88 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
89 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
91 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
92 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
93 #define HPTE_R_RPN_SHIFT 12
94 #define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
95 #define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
96 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
97 #define HPTE_R_N ASM_CONST(0x0000000000000004)
99 /* Values for PP (assumes Ks=0, Kp=1) */
100 /* pp0 will always be 0 for linux */
101 #define PP_RWXX 0 /* Supervisor read/write, User none */
102 #define PP_RWRX 1 /* Supervisor read/write, User read */
103 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
104 #define PP_RXRX 3 /* Supervisor read, User read */
113 extern hpte_t *htab_address;
114 extern unsigned long htab_hash_mask;
117 * Page size definition
119 * shift : is the "PAGE_SHIFT" value for that page size
120 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
121 * directly to a slbmte "vsid" value
122 * penc : is the HPTE encoding mask for the "LP" field:
127 unsigned int shift; /* number of bits */
128 unsigned int penc; /* HPTE encoding */
129 unsigned int tlbiel; /* tlbiel supported for that page size */
130 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
131 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
134 #endif /* __ASSEMBLY__ */
137 * The kernel use the constants below to index in the page sizes array.
138 * The use of fixed constants for this purpose is better for performances
139 * of the low level hash refill handlers.
141 * A non supported page size has a "shift" field set to 0
143 * Any new page size being implemented can get a new entry in here. Whether
144 * the kernel will use it or not is a different matter though. The actual page
145 * size used by hugetlbfs is not defined here and may be made variable
148 #define MMU_PAGE_4K 0 /* 4K */
149 #define MMU_PAGE_64K 1 /* 64K */
150 #define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
151 #define MMU_PAGE_1M 3 /* 1M */
152 #define MMU_PAGE_16M 4 /* 16M */
153 #define MMU_PAGE_16G 5 /* 16G */
154 #define MMU_PAGE_COUNT 6
159 * The current system page sizes
161 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
162 extern int mmu_linear_psize;
163 extern int mmu_virtual_psize;
165 #ifdef CONFIG_HUGETLB_PAGE
167 * The page size index of the huge pages for use by hugetlbfs
169 extern int mmu_huge_psize;
171 #endif /* CONFIG_HUGETLB_PAGE */
174 * This function sets the AVPN and L fields of the HPTE appropriately
177 static inline unsigned long hpte_encode_v(unsigned long va, int psize)
180 v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
181 v <<= HPTE_V_AVPN_SHIFT;
182 if (psize != MMU_PAGE_4K)
188 * This function sets the ARPN, and LP fields of the HPTE appropriately
189 * for the page size. We assume the pa is already "clean" that is properly
190 * aligned for the requested page size
192 static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
196 /* A 4K page needs no special encoding */
197 if (psize == MMU_PAGE_4K)
198 return pa & HPTE_R_RPN;
200 unsigned int penc = mmu_psize_defs[psize].penc;
201 unsigned int shift = mmu_psize_defs[psize].shift;
202 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
208 * This hashes a virtual address for a 256Mb segment only for now
211 static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
213 return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
216 extern int __hash_page_4K(unsigned long ea, unsigned long access,
217 unsigned long vsid, pte_t *ptep, unsigned long trap,
219 extern int __hash_page_64K(unsigned long ea, unsigned long access,
220 unsigned long vsid, pte_t *ptep, unsigned long trap,
223 extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
224 unsigned long ea, unsigned long vsid, int local,
227 extern void htab_finish_init(void);
228 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
229 unsigned long pstart, unsigned long mode,
232 extern void htab_initialize(void);
233 extern void htab_initialize_secondary(void);
234 extern void hpte_init_native(void);
235 extern void hpte_init_lpar(void);
236 extern void hpte_init_iSeries(void);
237 extern void mm_init_ppc64(void);
239 extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
240 unsigned long va, unsigned long prpn,
241 unsigned long rflags,
242 unsigned long vflags, int psize);
244 extern long native_hpte_insert(unsigned long hpte_group,
245 unsigned long va, unsigned long prpn,
246 unsigned long rflags,
247 unsigned long vflags, int psize);
249 extern long iSeries_hpte_insert(unsigned long hpte_group,
250 unsigned long va, unsigned long prpn,
251 unsigned long rflags,
252 unsigned long vflags, int psize);
254 extern void stabs_alloc(void);
255 extern void slb_initialize(void);
256 extern void stab_initialize(unsigned long stab);
258 #endif /* __ASSEMBLY__ */
263 * We first generate a 36-bit "proto-VSID". For kernel addresses this
264 * is equal to the ESID, for user addresses it is:
265 * (context << 15) | (esid & 0x7fff)
267 * The two forms are distinguishable because the top bit is 0 for user
268 * addresses, whereas the top two bits are 1 for kernel addresses.
269 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
272 * The proto-VSIDs are then scrambled into real VSIDs with the
273 * multiplicative hash:
275 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
276 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
277 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
279 * This scramble is only well defined for proto-VSIDs below
280 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
281 * reserved. VSID_MULTIPLIER is prime, so in particular it is
282 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
283 * Because the modulus is 2^n-1 we can compute it efficiently without
284 * a divide or extra multiply (see below).
286 * This scheme has several advantages over older methods:
288 * - We have VSIDs allocated for every kernel address
289 * (i.e. everything above 0xC000000000000000), except the very top
290 * segment, which simplifies several things.
292 * - We allow for 15 significant bits of ESID and 20 bits of
293 * context for user addresses. i.e. 8T (43 bits) of address space for
294 * up to 1M contexts (although the page table structure and context
295 * allocation will need changes to take advantage of this).
297 * - The scramble function gives robust scattering in the hash
298 * table (at least based on some initial results). The previous
299 * method was more susceptible to pathological cases giving excessive
303 * WARNING - If you change these you must make sure the asm
304 * implementations in slb_allocate (slb_low.S), do_stab_bolted
305 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
307 * You'll also need to change the precomputed VSID values in head.S
308 * which are used by the iSeries firmware.
311 #define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
313 #define VSID_MODULUS ((1UL<<VSID_BITS)-1)
315 #define CONTEXT_BITS 19
316 #define USER_ESID_BITS 16
318 #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
321 * This macro generates asm code to compute the VSID scramble
322 * function. Used in slb_allocate() and do_stab_bolted. The function
323 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
325 * rt = register continaing the proto-VSID and into which the
326 * VSID will be stored
327 * rx = scratch register (clobbered)
329 * - rt and rx must be different registers
330 * - The answer will end up in the low 36 bits of rt. The higher
331 * bits may contain other garbage, so you may need to mask the
334 #define ASM_VSID_SCRAMBLE(rt, rx) \
335 lis rx,VSID_MULTIPLIER@h; \
336 ori rx,rx,VSID_MULTIPLIER@l; \
337 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
339 srdi rx,rt,VSID_BITS; \
340 clrldi rt,rt,(64-VSID_BITS); \
341 add rt,rt,rx; /* add high and low bits */ \
342 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
343 * 2^36-1+2^28-1. That in particular means that if r3 >= \
344 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
345 * the bit clear, r3 already has the answer we want, if it \
346 * doesn't, the answer is the low 36 bits of r3+1. So in all \
347 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
349 srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
355 typedef unsigned long mm_context_id_t;
359 #ifdef CONFIG_HUGETLB_PAGE
360 u16 low_htlb_areas, high_htlb_areas;
365 static inline unsigned long vsid_scramble(unsigned long protovsid)
368 /* The code below is equivalent to this function for arguments
369 * < 2^VSID_BITS, which is all this should ever be called
370 * with. However gcc is not clever enough to compute the
371 * modulus (2^n-1) without a second multiply. */
372 return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
376 x = protovsid * VSID_MULTIPLIER;
377 x = (x >> VSID_BITS) + (x & VSID_MODULUS);
378 return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
382 /* This is only valid for addresses >= KERNELBASE */
383 static inline unsigned long get_kernel_vsid(unsigned long ea)
385 return vsid_scramble(ea >> SID_SHIFT);
388 /* This is only valid for user addresses (which are below 2^41) */
389 static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
391 return vsid_scramble((context << USER_ESID_BITS)
392 | (ea >> SID_SHIFT));
395 #define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
396 #define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
398 /* Physical address used by some IO functions */
399 typedef unsigned long phys_addr_t;
402 #endif /* __ASSEMBLY */
404 #endif /* CONFIG_PPC64 */
405 #endif /* _ASM_POWERPC_MMU_H_ */