1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
4 #include <asm/asm-compat.h>
6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
17 #define PPC_FEATURE_NO_TB 0x00100000
18 #define PPC_FEATURE_POWER4 0x00080000
19 #define PPC_FEATURE_POWER5 0x00040000
20 #define PPC_FEATURE_POWER5_PLUS 0x00020000
21 #define PPC_FEATURE_CELL 0x00010000
22 #define PPC_FEATURE_BOOKE 0x00008000
23 #define PPC_FEATURE_SMT 0x00004000
24 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25 #define PPC_FEATURE_ARCH_2_05 0x00001000
27 #define PPC_FEATURE_TRUE_LE 0x00000002
28 #define PPC_FEATURE_PPC_LE 0x00000001
33 /* This structure can grow, it's real size is used by head.S code
34 * via the mkdefs mechanism.
38 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
39 typedef void (*cpu_restore_t)(void);
41 enum powerpc_oprofile_type {
42 PPC_OPROFILE_INVALID = 0,
43 PPC_OPROFILE_RS64 = 1,
44 PPC_OPROFILE_POWER4 = 2,
46 PPC_OPROFILE_BOOKE = 4,
50 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
51 unsigned int pvr_mask;
52 unsigned int pvr_value;
55 unsigned long cpu_features; /* Kernel features */
56 unsigned int cpu_user_features; /* Userland features */
58 /* cache line sizes */
59 unsigned int icache_bsize;
60 unsigned int dcache_bsize;
62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
65 /* this is called to initialize various CPU bits like L1 cache,
66 * BHT, SPD, etc... from head.S before branching to identify_machine
68 cpu_setup_t cpu_setup;
69 /* Used to restore cpu setup on secondary processors and at resume */
70 cpu_restore_t cpu_restore;
72 /* Used by oprofile userspace to select the right counters */
73 char *oprofile_cpu_type;
75 /* Processor specific oprofile operations */
76 enum powerpc_oprofile_type oprofile_type;
78 /* Bit locations inside the mmcra change */
79 unsigned long oprofile_mmcra_sihv;
80 unsigned long oprofile_mmcra_sipr;
82 /* Bits to clear during an oprofile exception */
83 unsigned long oprofile_mmcra_clear;
85 /* Name of processor class, for the ELF AT_PLATFORM entry */
89 extern struct cpu_spec *cur_cpu_spec;
91 extern void identify_cpu(unsigned long offset, unsigned long cpu);
92 extern void do_cpu_ftr_fixups(unsigned long offset);
94 #endif /* __ASSEMBLY__ */
96 /* CPU kernel features */
98 /* Retain the 32b definitions all use bottom half of word */
99 #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
100 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
101 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
102 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
103 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
104 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
105 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
106 #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
107 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
108 #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
109 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
110 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
111 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
112 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
113 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
114 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
115 #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
116 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
117 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
118 #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
119 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
120 #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
121 #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
124 * Add the 64-bit processor unique features in the top half of the word;
125 * on 32-bit, make the names available but defined to be 0.
128 #define LONG_ASM_CONST(x) ASM_CONST(x)
130 #define LONG_ASM_CONST(x) 0
133 #define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
134 #define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
135 #define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
136 #define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
137 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
138 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
139 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
140 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
141 #define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
142 #define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
143 #define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
144 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
145 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
149 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
150 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
151 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
153 /* iSeries doesn't support large pages */
154 #ifdef CONFIG_PPC_ISERIES
155 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
157 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
158 #endif /* CONFIG_PPC_ISERIES */
160 /* We only set the altivec features if the kernel was compiled with altivec
163 #ifdef CONFIG_ALTIVEC
164 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
165 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
167 #define CPU_FTR_ALTIVEC_COMP 0
168 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
171 /* We need to mark all pages as being coherent if we're SMP or we
172 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
173 * it for PCI "streaming/prefetch" to work properly.
175 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
176 || defined(CONFIG_PPC_83xx)
177 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
179 #define CPU_FTR_COMMON 0
182 /* The powersave features NAP & DOZE seems to confuse BDI when
183 debugging. So if a BDI is used, disable theses
185 #ifndef CONFIG_BDI_SWITCH
186 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
187 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
189 #define CPU_FTR_MAYBE_CAN_DOZE 0
190 #define CPU_FTR_MAYBE_CAN_NAP 0
193 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
194 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
195 !defined(CONFIG_BOOKE))
197 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
198 #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
199 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
200 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
201 #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
202 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
204 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
205 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
206 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
207 #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
208 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
209 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
211 #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
213 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
215 #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
216 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
217 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
218 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
219 #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
220 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
221 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
222 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
223 #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
224 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
225 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
226 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
227 #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
228 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
229 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
230 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
231 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
232 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
233 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
234 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
235 #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
236 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
237 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
238 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
239 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
240 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
241 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
242 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
243 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
245 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
246 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
247 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
248 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
249 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
251 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
252 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
253 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
254 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
256 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
257 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
258 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
259 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
261 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
262 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
263 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
264 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
265 #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
268 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
269 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
270 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
271 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
273 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
274 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
275 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
276 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
277 #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
279 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
280 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
281 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
282 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
283 #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
285 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
286 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
287 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
288 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
289 #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
290 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
291 #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
292 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
293 #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
294 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
296 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
297 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
298 #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
299 #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
300 CPU_FTR_NODSISRALIGN)
301 #define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
302 CPU_FTR_NODSISRALIGN)
303 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
304 #define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
305 CPU_FTR_NODSISRALIGN)
306 #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
307 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
308 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
310 #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
311 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
312 #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
313 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
314 CPU_FTR_MMCRA | CPU_FTR_CTRL)
315 #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
316 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA)
317 #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
318 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
319 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
320 #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
321 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
322 CPU_FTR_MMCRA | CPU_FTR_SMT | \
323 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
325 #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
326 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
327 CPU_FTR_MMCRA | CPU_FTR_SMT | \
328 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
329 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
330 #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
331 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
332 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
333 CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
334 #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
335 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
339 #define CPU_FTRS_POSSIBLE \
340 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
341 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
342 CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
347 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
348 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
349 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
350 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
351 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
352 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
353 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
354 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
356 CPU_FTRS_GENERIC_32 |
371 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
375 #endif /* __powerpc64__ */
378 #define CPU_FTRS_ALWAYS \
379 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
380 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
381 CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
386 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
387 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
388 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
389 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
390 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
391 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
392 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
393 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
395 CPU_FTRS_GENERIC_32 &
410 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
414 #endif /* __powerpc64__ */
416 static inline int cpu_has_feature(unsigned long feature)
418 return (CPU_FTRS_ALWAYS & feature) ||
420 & cur_cpu_spec->cpu_features
424 #endif /* !__ASSEMBLY__ */
428 #define BEGIN_FTR_SECTION 98:
430 #ifndef __powerpc64__
431 #define END_FTR_SECTION(msk, val) \
433 .section __ftr_fixup,"a"; \
440 #else /* __powerpc64__ */
441 #define END_FTR_SECTION(msk, val) \
443 .section __ftr_fixup,"a"; \
450 #endif /* __powerpc64__ */
452 #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
453 #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
454 #endif /* __ASSEMBLY__ */
456 #endif /* __KERNEL__ */
457 #endif /* __ASM_POWERPC_CPUTABLE_H */