1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
4 #include <asm/asm-compat.h>
6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
17 #define PPC_FEATURE_NO_TB 0x00100000
18 #define PPC_FEATURE_POWER4 0x00080000
19 #define PPC_FEATURE_POWER5 0x00040000
20 #define PPC_FEATURE_POWER5_PLUS 0x00020000
21 #define PPC_FEATURE_CELL 0x00010000
22 #define PPC_FEATURE_BOOKE 0x00008000
23 #define PPC_FEATURE_SMT 0x00004000
24 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25 #define PPC_FEATURE_ARCH_2_05 0x00001000
26 #define PPC_FEATURE_PA6T 0x00000800
28 #define PPC_FEATURE_TRUE_LE 0x00000002
29 #define PPC_FEATURE_PPC_LE 0x00000001
34 /* This structure can grow, it's real size is used by head.S code
35 * via the mkdefs mechanism.
39 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
40 typedef void (*cpu_restore_t)(void);
42 enum powerpc_oprofile_type {
43 PPC_OPROFILE_INVALID = 0,
44 PPC_OPROFILE_RS64 = 1,
45 PPC_OPROFILE_POWER4 = 2,
47 PPC_OPROFILE_BOOKE = 4,
51 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
52 unsigned int pvr_mask;
53 unsigned int pvr_value;
56 unsigned long cpu_features; /* Kernel features */
57 unsigned int cpu_user_features; /* Userland features */
59 /* cache line sizes */
60 unsigned int icache_bsize;
61 unsigned int dcache_bsize;
63 /* number of performance monitor counters */
64 unsigned int num_pmcs;
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
69 cpu_setup_t cpu_setup;
70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
76 /* Processor specific oprofile operations */
77 enum powerpc_oprofile_type oprofile_type;
79 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
86 /* Name of processor class, for the ELF AT_PLATFORM entry */
90 extern struct cpu_spec *cur_cpu_spec;
92 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
94 extern struct cpu_spec *identify_cpu(unsigned long offset);
95 extern void do_feature_fixups(unsigned long offset, unsigned long value,
96 void *fixup_start, void *fixup_end);
98 #endif /* __ASSEMBLY__ */
100 /* CPU kernel features */
102 /* Retain the 32b definitions all use bottom half of word */
103 #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
104 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
105 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
106 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
107 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
108 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
109 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
110 #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
111 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
112 #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
113 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
114 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
115 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
116 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
117 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
118 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
119 #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
120 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
121 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
122 #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
123 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
124 #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
125 #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
128 * Add the 64-bit processor unique features in the top half of the word;
129 * on 32-bit, make the names available but defined to be 0.
132 #define LONG_ASM_CONST(x) ASM_CONST(x)
134 #define LONG_ASM_CONST(x) 0
137 #define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
138 #define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
139 #define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
140 #define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
141 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
142 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
143 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
144 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
145 #define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
146 #define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
147 #define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
148 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
149 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
153 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
154 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
155 CPU_FTR_NODSISRALIGN)
157 /* iSeries doesn't support large pages */
158 #ifdef CONFIG_PPC_ISERIES
159 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
161 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
162 #endif /* CONFIG_PPC_ISERIES */
164 /* We only set the altivec features if the kernel was compiled with altivec
167 #ifdef CONFIG_ALTIVEC
168 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
169 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
171 #define CPU_FTR_ALTIVEC_COMP 0
172 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
175 /* We need to mark all pages as being coherent if we're SMP or we
176 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
177 * it for PCI "streaming/prefetch" to work properly.
179 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
180 || defined(CONFIG_PPC_83xx)
181 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
183 #define CPU_FTR_COMMON 0
186 /* The powersave features NAP & DOZE seems to confuse BDI when
187 debugging. So if a BDI is used, disable theses
189 #ifndef CONFIG_BDI_SWITCH
190 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
191 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
193 #define CPU_FTR_MAYBE_CAN_DOZE 0
194 #define CPU_FTR_MAYBE_CAN_NAP 0
197 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
198 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
199 !defined(CONFIG_BOOKE))
201 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
202 #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
203 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
204 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
205 #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
206 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
208 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
209 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
210 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
211 #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
213 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
215 #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
216 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
217 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
219 #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
220 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
221 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
222 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
223 #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
224 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
225 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
226 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
227 #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
228 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
229 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
230 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
231 #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
232 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
233 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
234 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
235 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
236 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
237 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
238 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
239 #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
240 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
241 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
242 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
243 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
244 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
245 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
246 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
247 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
250 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
251 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
252 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
253 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
255 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
256 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
257 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
258 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
260 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
261 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
262 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
263 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
265 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
266 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
267 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
268 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
269 #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
271 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
272 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
273 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
274 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
275 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
277 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
278 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
279 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
280 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
281 #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
283 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
284 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
285 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
286 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
287 #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
289 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
290 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
291 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
292 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
293 #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
294 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
295 #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
296 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
297 #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
298 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
300 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
301 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
302 #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
303 #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
304 CPU_FTR_NODSISRALIGN)
305 #define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
306 CPU_FTR_NODSISRALIGN)
307 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
308 #define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
309 CPU_FTR_NODSISRALIGN)
310 #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
311 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
312 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
314 #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
315 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
316 #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
317 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
318 CPU_FTR_MMCRA | CPU_FTR_CTRL)
319 #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
320 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
322 #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
323 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
324 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
325 #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
326 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
327 CPU_FTR_MMCRA | CPU_FTR_SMT | \
328 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
330 #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
331 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
332 CPU_FTR_MMCRA | CPU_FTR_SMT | \
333 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
334 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
335 #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
336 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
337 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
338 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
339 #define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
340 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
341 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
342 CPU_FTR_PURR | CPU_FTR_REAL_LE)
343 #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
344 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
348 #define CPU_FTRS_POSSIBLE \
349 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
350 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
351 CPU_FTRS_CELL | CPU_FTRS_PA6T)
356 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
357 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
358 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
359 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
360 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
361 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
362 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
363 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
365 CPU_FTRS_GENERIC_32 |
380 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
384 #endif /* __powerpc64__ */
387 #define CPU_FTRS_ALWAYS \
388 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
389 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
390 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
395 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
396 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
397 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
398 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
399 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
400 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
401 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
402 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
404 CPU_FTRS_GENERIC_32 &
419 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
423 #endif /* __powerpc64__ */
425 static inline int cpu_has_feature(unsigned long feature)
427 return (CPU_FTRS_ALWAYS & feature) ||
429 & cur_cpu_spec->cpu_features
433 #endif /* !__ASSEMBLY__ */
437 #define BEGIN_FTR_SECTION_NESTED(label) label:
438 #define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(98)
440 #ifndef __powerpc64__
441 #define END_FTR_SECTION_NESTED(msk, val, label) \
443 .section __ftr_fixup,"a"; \
450 #else /* __powerpc64__ */
451 #define END_FTR_SECTION_NESTED(msk, val, label) \
453 .section __ftr_fixup,"a"; \
460 #endif /* __powerpc64__ */
462 #define END_FTR_SECTION(msk, val) \
463 END_FTR_SECTION_NESTED(msk, val, 98)
465 #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
466 #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
467 #endif /* __ASSEMBLY__ */
469 #endif /* __KERNEL__ */
470 #endif /* __ASM_POWERPC_CPUTABLE_H */