2 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
3 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
4 * Copyright (C) 1999 SuSE GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #ifndef _PARISC_ASSEMBLY_H
22 #define _PARISC_ASSEMBLY_H
24 #define CALLEE_FLOAT_FRAME_SIZE 80
33 #define FRAME_SIZE 128
34 #define CALLEE_REG_FRAME_SIZE 144
44 #define CALLEE_REG_FRAME_SIZE 128
46 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
63 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
64 * work around that for now... */
68 #include <asm/asm-offsets.h>
71 #include <asm/asmregs.h>
78 * We provide two versions of each macro to convert from physical
79 * to virtual and vice versa. The "_r1" versions take one argument
80 * register, but trashes r1 to do the conversion. The other
81 * version takes two arguments: a src and destination register.
82 * However, the source and destination registers can not be
86 .macro tophys grvirt, grphys
87 ldil L%(__PAGE_OFFSET), \grphys
88 sub \grvirt, \grphys, \grphys
91 .macro tovirt grphys, grvirt
92 ldil L%(__PAGE_OFFSET), \grvirt
93 add \grphys, \grvirt, \grvirt
97 ldil L%(__PAGE_OFFSET), %r1
102 ldil L%(__PAGE_OFFSET), %r1
118 /* Shift Left - note the r and t can NOT be the same! */
120 dep,z \r, 31-\sa, 32-\sa, \t
123 /* The PA 2.0 shift left */
125 depw,z \r, 31-\sa, 32-\sa, \t
128 /* And the PA 2.0W shift left */
130 depd,z \r, 63-\sa, 64-\sa, \t
133 /* Shift Right - note the r and t can NOT be the same! */
135 extru \r, 31-\sa, 32-\sa, \t
138 /* pa20w version of shift right */
140 extrd,u \r, 63-\sa, 64-\sa, \t
143 /* load 32-bit 'value' into 'reg' compensating for the ldil
144 * sign-extension when running in wide mode.
145 * WARNING!! neither 'value' nor 'reg' can be expressions
146 * containing '.'!!!! */
147 .macro load32 value, reg
149 ldo R%\value(\reg), \reg
155 ldo R%__gp(%r27), %r27
157 ldil L%$global$, %r27
158 ldo R%$global$(%r27), %r27
162 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
163 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
164 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
165 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
167 .macro save_general regs
168 STREG %r1, PT_GR1 (\regs)
169 STREG %r2, PT_GR2 (\regs)
170 STREG %r3, PT_GR3 (\regs)
171 STREG %r4, PT_GR4 (\regs)
172 STREG %r5, PT_GR5 (\regs)
173 STREG %r6, PT_GR6 (\regs)
174 STREG %r7, PT_GR7 (\regs)
175 STREG %r8, PT_GR8 (\regs)
176 STREG %r9, PT_GR9 (\regs)
177 STREG %r10, PT_GR10(\regs)
178 STREG %r11, PT_GR11(\regs)
179 STREG %r12, PT_GR12(\regs)
180 STREG %r13, PT_GR13(\regs)
181 STREG %r14, PT_GR14(\regs)
182 STREG %r15, PT_GR15(\regs)
183 STREG %r16, PT_GR16(\regs)
184 STREG %r17, PT_GR17(\regs)
185 STREG %r18, PT_GR18(\regs)
186 STREG %r19, PT_GR19(\regs)
187 STREG %r20, PT_GR20(\regs)
188 STREG %r21, PT_GR21(\regs)
189 STREG %r22, PT_GR22(\regs)
190 STREG %r23, PT_GR23(\regs)
191 STREG %r24, PT_GR24(\regs)
192 STREG %r25, PT_GR25(\regs)
193 /* r26 is saved in get_stack and used to preserve a value across virt_map */
194 STREG %r27, PT_GR27(\regs)
195 STREG %r28, PT_GR28(\regs)
196 /* r29 is saved in get_stack and used to point to saved registers */
197 /* r30 stack pointer saved in get_stack */
198 STREG %r31, PT_GR31(\regs)
201 .macro rest_general regs
202 /* r1 used as a temp in rest_stack and is restored there */
203 LDREG PT_GR2 (\regs), %r2
204 LDREG PT_GR3 (\regs), %r3
205 LDREG PT_GR4 (\regs), %r4
206 LDREG PT_GR5 (\regs), %r5
207 LDREG PT_GR6 (\regs), %r6
208 LDREG PT_GR7 (\regs), %r7
209 LDREG PT_GR8 (\regs), %r8
210 LDREG PT_GR9 (\regs), %r9
211 LDREG PT_GR10(\regs), %r10
212 LDREG PT_GR11(\regs), %r11
213 LDREG PT_GR12(\regs), %r12
214 LDREG PT_GR13(\regs), %r13
215 LDREG PT_GR14(\regs), %r14
216 LDREG PT_GR15(\regs), %r15
217 LDREG PT_GR16(\regs), %r16
218 LDREG PT_GR17(\regs), %r17
219 LDREG PT_GR18(\regs), %r18
220 LDREG PT_GR19(\regs), %r19
221 LDREG PT_GR20(\regs), %r20
222 LDREG PT_GR21(\regs), %r21
223 LDREG PT_GR22(\regs), %r22
224 LDREG PT_GR23(\regs), %r23
225 LDREG PT_GR24(\regs), %r24
226 LDREG PT_GR25(\regs), %r25
227 LDREG PT_GR26(\regs), %r26
228 LDREG PT_GR27(\regs), %r27
229 LDREG PT_GR28(\regs), %r28
230 /* r29 points to register save area, and is restored in rest_stack */
231 /* r30 stack pointer restored in rest_stack */
232 LDREG PT_GR31(\regs), %r31
236 fstd,ma %fr0, 8(\regs)
237 fstd,ma %fr1, 8(\regs)
238 fstd,ma %fr2, 8(\regs)
239 fstd,ma %fr3, 8(\regs)
240 fstd,ma %fr4, 8(\regs)
241 fstd,ma %fr5, 8(\regs)
242 fstd,ma %fr6, 8(\regs)
243 fstd,ma %fr7, 8(\regs)
244 fstd,ma %fr8, 8(\regs)
245 fstd,ma %fr9, 8(\regs)
246 fstd,ma %fr10, 8(\regs)
247 fstd,ma %fr11, 8(\regs)
248 fstd,ma %fr12, 8(\regs)
249 fstd,ma %fr13, 8(\regs)
250 fstd,ma %fr14, 8(\regs)
251 fstd,ma %fr15, 8(\regs)
252 fstd,ma %fr16, 8(\regs)
253 fstd,ma %fr17, 8(\regs)
254 fstd,ma %fr18, 8(\regs)
255 fstd,ma %fr19, 8(\regs)
256 fstd,ma %fr20, 8(\regs)
257 fstd,ma %fr21, 8(\regs)
258 fstd,ma %fr22, 8(\regs)
259 fstd,ma %fr23, 8(\regs)
260 fstd,ma %fr24, 8(\regs)
261 fstd,ma %fr25, 8(\regs)
262 fstd,ma %fr26, 8(\regs)
263 fstd,ma %fr27, 8(\regs)
264 fstd,ma %fr28, 8(\regs)
265 fstd,ma %fr29, 8(\regs)
266 fstd,ma %fr30, 8(\regs)
272 fldd,mb -8(\regs), %fr30
273 fldd,mb -8(\regs), %fr29
274 fldd,mb -8(\regs), %fr28
275 fldd,mb -8(\regs), %fr27
276 fldd,mb -8(\regs), %fr26
277 fldd,mb -8(\regs), %fr25
278 fldd,mb -8(\regs), %fr24
279 fldd,mb -8(\regs), %fr23
280 fldd,mb -8(\regs), %fr22
281 fldd,mb -8(\regs), %fr21
282 fldd,mb -8(\regs), %fr20
283 fldd,mb -8(\regs), %fr19
284 fldd,mb -8(\regs), %fr18
285 fldd,mb -8(\regs), %fr17
286 fldd,mb -8(\regs), %fr16
287 fldd,mb -8(\regs), %fr15
288 fldd,mb -8(\regs), %fr14
289 fldd,mb -8(\regs), %fr13
290 fldd,mb -8(\regs), %fr12
291 fldd,mb -8(\regs), %fr11
292 fldd,mb -8(\regs), %fr10
293 fldd,mb -8(\regs), %fr9
294 fldd,mb -8(\regs), %fr8
295 fldd,mb -8(\regs), %fr7
296 fldd,mb -8(\regs), %fr6
297 fldd,mb -8(\regs), %fr5
298 fldd,mb -8(\regs), %fr4
299 fldd,mb -8(\regs), %fr3
300 fldd,mb -8(\regs), %fr2
301 fldd,mb -8(\regs), %fr1
302 fldd,mb -8(\regs), %fr0
305 .macro callee_save_float
306 fstd,ma %fr12, 8(%r30)
307 fstd,ma %fr13, 8(%r30)
308 fstd,ma %fr14, 8(%r30)
309 fstd,ma %fr15, 8(%r30)
310 fstd,ma %fr16, 8(%r30)
311 fstd,ma %fr17, 8(%r30)
312 fstd,ma %fr18, 8(%r30)
313 fstd,ma %fr19, 8(%r30)
314 fstd,ma %fr20, 8(%r30)
315 fstd,ma %fr21, 8(%r30)
318 .macro callee_rest_float
319 fldd,mb -8(%r30), %fr21
320 fldd,mb -8(%r30), %fr20
321 fldd,mb -8(%r30), %fr19
322 fldd,mb -8(%r30), %fr18
323 fldd,mb -8(%r30), %fr17
324 fldd,mb -8(%r30), %fr16
325 fldd,mb -8(%r30), %fr15
326 fldd,mb -8(%r30), %fr14
327 fldd,mb -8(%r30), %fr13
328 fldd,mb -8(%r30), %fr12
333 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
371 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
374 #else /* ! __LP64__ */
377 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
415 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
417 #endif /* ! __LP64__ */
419 .macro save_specials regs
421 SAVE_SP (%sr0, PT_SR0 (\regs))
422 SAVE_SP (%sr1, PT_SR1 (\regs))
423 SAVE_SP (%sr2, PT_SR2 (\regs))
424 SAVE_SP (%sr3, PT_SR3 (\regs))
425 SAVE_SP (%sr4, PT_SR4 (\regs))
426 SAVE_SP (%sr5, PT_SR5 (\regs))
427 SAVE_SP (%sr6, PT_SR6 (\regs))
428 SAVE_SP (%sr7, PT_SR7 (\regs))
430 SAVE_CR (%cr17, PT_IASQ0(\regs))
432 SAVE_CR (%cr17, PT_IASQ1(\regs))
434 SAVE_CR (%cr18, PT_IAOQ0(\regs))
436 SAVE_CR (%cr18, PT_IAOQ1(\regs))
439 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0
440 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
441 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise
442 * we lose the 6th bit on a save/restore over interrupt.
445 STREG %r1, PT_SAR (\regs)
447 SAVE_CR (%cr11, PT_SAR (\regs))
449 SAVE_CR (%cr19, PT_IIR (\regs))
452 * Code immediately following this macro (in intr_save) relies
453 * on r8 containing ipsw.
456 STREG %r8, PT_PSW(\regs)
459 .macro rest_specials regs
461 REST_SP (%sr0, PT_SR0 (\regs))
462 REST_SP (%sr1, PT_SR1 (\regs))
463 REST_SP (%sr2, PT_SR2 (\regs))
464 REST_SP (%sr3, PT_SR3 (\regs))
465 REST_SP (%sr4, PT_SR4 (\regs))
466 REST_SP (%sr5, PT_SR5 (\regs))
467 REST_SP (%sr6, PT_SR6 (\regs))
468 REST_SP (%sr7, PT_SR7 (\regs))
470 REST_CR (%cr17, PT_IASQ0(\regs))
471 REST_CR (%cr17, PT_IASQ1(\regs))
473 REST_CR (%cr18, PT_IAOQ0(\regs))
474 REST_CR (%cr18, PT_IAOQ1(\regs))
476 REST_CR (%cr11, PT_SAR (\regs))
478 REST_CR (%cr22, PT_PSW (\regs))
482 /* First step to create a "relied upon translation"
483 * See PA 2.0 Arch. page F-4 and F-5.
485 * The ssm was originally necessary due to a "PCxT bug".
486 * But someone decided it needed to be added to the architecture
487 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
488 * It's been carried forward into PA 2.0 Arch as well. :^(
490 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
491 * rsm/ssm prevents the ifetch unit from speculatively fetching
492 * instructions past this line in the code stream.
493 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
506 #endif /* __ASSEMBLY__ */