2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2000 Toshiba Corporation
8 #ifndef __ASM_TXX9_TX3927_H
9 #define __ASM_TXX9_TX3927_H
11 #include <asm/txx9/txx927.h>
13 #define TX3927_REG_BASE 0xfffe0000UL
14 #define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
15 #define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
16 #define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
17 #define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
18 #define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
19 #define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
20 #define TX3927_NR_TMR 3
21 #define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
22 #define TX3927_NR_SIO 2
23 #define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
24 #define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
26 struct tx3927_sdramc_reg {
27 volatile unsigned long cr[8];
28 volatile unsigned long tr[3];
29 volatile unsigned long cmd;
30 volatile unsigned long smrs[2];
33 struct tx3927_romc_reg {
34 volatile unsigned long cr[8];
37 struct tx3927_dma_reg {
38 struct tx3927_dma_ch_reg {
39 volatile unsigned long cha;
40 volatile unsigned long sar;
41 volatile unsigned long dar;
42 volatile unsigned long cntr;
43 volatile unsigned long sair;
44 volatile unsigned long dair;
45 volatile unsigned long ccr;
46 volatile unsigned long csr;
48 volatile unsigned long dbr[8];
49 volatile unsigned long tdhr;
50 volatile unsigned long mcr;
51 volatile unsigned long unused0;
54 #include <asm/byteorder.h>
57 #define endian_def_s2(e1, e2) \
58 volatile unsigned short e1, e2
59 #define endian_def_sb2(e1, e2, e3) \
60 volatile unsigned short e1;volatile unsigned char e2, e3
61 #define endian_def_b2s(e1, e2, e3) \
62 volatile unsigned char e1, e2;volatile unsigned short e3
63 #define endian_def_b4(e1, e2, e3, e4) \
64 volatile unsigned char e1, e2, e3, e4
66 #define endian_def_s2(e1, e2) \
67 volatile unsigned short e2, e1
68 #define endian_def_sb2(e1, e2, e3) \
69 volatile unsigned char e3, e2;volatile unsigned short e1
70 #define endian_def_b2s(e1, e2, e3) \
71 volatile unsigned short e3;volatile unsigned char e2, e1
72 #define endian_def_b4(e1, e2, e3, e4) \
73 volatile unsigned char e4, e3, e2, e1
76 struct tx3927_pcic_reg {
77 endian_def_s2(did, vid);
78 endian_def_s2(pcistat, pcicmd);
79 endian_def_b4(cc, scc, rpli, rid);
80 endian_def_b4(unused0, ht, mlt, cls);
81 volatile unsigned long ioba; /* +10 */
82 volatile unsigned long mba;
83 volatile unsigned long unused1[5];
84 endian_def_s2(svid, ssvid);
85 volatile unsigned long unused2; /* +30 */
86 endian_def_sb2(unused3, unused4, capptr);
87 volatile unsigned long unused5;
88 endian_def_b4(ml, mg, ip, il);
89 volatile unsigned long unused6; /* +40 */
90 volatile unsigned long istat;
91 volatile unsigned long iim;
92 volatile unsigned long rrt;
93 volatile unsigned long unused7[3]; /* +50 */
94 volatile unsigned long ipbmma;
95 volatile unsigned long ipbioma; /* +60 */
96 volatile unsigned long ilbmma;
97 volatile unsigned long ilbioma;
98 volatile unsigned long unused8[9];
99 volatile unsigned long tc; /* +90 */
100 volatile unsigned long tstat;
101 volatile unsigned long tim;
102 volatile unsigned long tccmd;
103 volatile unsigned long pcirrt; /* +a0 */
104 volatile unsigned long pcirrt_cmd;
105 volatile unsigned long pcirrdt;
106 volatile unsigned long unused9[3];
107 volatile unsigned long tlboap;
108 volatile unsigned long tlbiap;
109 volatile unsigned long tlbmma; /* +c0 */
110 volatile unsigned long tlbioma;
111 volatile unsigned long sc_msg;
112 volatile unsigned long sc_be;
113 volatile unsigned long tbl; /* +d0 */
114 volatile unsigned long unused10[3];
115 volatile unsigned long pwmng; /* +e0 */
116 volatile unsigned long pwmngs;
117 volatile unsigned long unused11[6];
118 volatile unsigned long req_trace; /* +100 */
119 volatile unsigned long pbapmc;
120 volatile unsigned long pbapms;
121 volatile unsigned long pbapmim;
122 volatile unsigned long bm; /* +110 */
123 volatile unsigned long cpcibrs;
124 volatile unsigned long cpcibgs;
125 volatile unsigned long pbacs;
126 volatile unsigned long iobas; /* +120 */
127 volatile unsigned long mbas;
128 volatile unsigned long lbc;
129 volatile unsigned long lbstat;
130 volatile unsigned long lbim; /* +130 */
131 volatile unsigned long pcistatim;
132 volatile unsigned long ica;
133 volatile unsigned long icd;
134 volatile unsigned long iiadp; /* +140 */
135 volatile unsigned long iscdp;
136 volatile unsigned long mmas;
137 volatile unsigned long iomas;
138 volatile unsigned long ipciaddr; /* +150 */
139 volatile unsigned long ipcidata;
140 volatile unsigned long ipcibe;
143 struct tx3927_ccfg_reg {
144 volatile unsigned long ccfg;
145 volatile unsigned long crir;
146 volatile unsigned long pcfg;
147 volatile unsigned long tear;
148 volatile unsigned long pdcr;
163 #define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
164 #define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
165 #define TX3927_DMA_MCR_RSFIF 0x00000080
166 #define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
167 #define TX3927_DMA_MCR_LE 0x00000004
168 #define TX3927_DMA_MCR_RPRT 0x00000002
169 #define TX3927_DMA_MCR_MSTEN 0x00000001
172 #define TX3927_DMA_CCR_DBINH 0x04000000
173 #define TX3927_DMA_CCR_SBINH 0x02000000
174 #define TX3927_DMA_CCR_CHRST 0x01000000
175 #define TX3927_DMA_CCR_RVBYTE 0x00800000
176 #define TX3927_DMA_CCR_ACKPOL 0x00400000
177 #define TX3927_DMA_CCR_REQPL 0x00200000
178 #define TX3927_DMA_CCR_EGREQ 0x00100000
179 #define TX3927_DMA_CCR_CHDN 0x00080000
180 #define TX3927_DMA_CCR_DNCTL 0x00060000
181 #define TX3927_DMA_CCR_EXTRQ 0x00010000
182 #define TX3927_DMA_CCR_INTRQD 0x0000e000
183 #define TX3927_DMA_CCR_INTENE 0x00001000
184 #define TX3927_DMA_CCR_INTENC 0x00000800
185 #define TX3927_DMA_CCR_INTENT 0x00000400
186 #define TX3927_DMA_CCR_CHNEN 0x00000200
187 #define TX3927_DMA_CCR_XFACT 0x00000100
188 #define TX3927_DMA_CCR_SNOP 0x00000080
189 #define TX3927_DMA_CCR_DSTINC 0x00000040
190 #define TX3927_DMA_CCR_SRCINC 0x00000020
191 #define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
192 #define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
193 #define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
194 #define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
195 #define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
196 #define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
197 #define TX3927_DMA_CCR_MEMIO 0x00000002
198 #define TX3927_DMA_CCR_ONEAD 0x00000001
201 #define TX3927_DMA_CSR_CHNACT 0x00000100
202 #define TX3927_DMA_CSR_ABCHC 0x00000080
203 #define TX3927_DMA_CSR_NCHNC 0x00000040
204 #define TX3927_DMA_CSR_NTRNFC 0x00000020
205 #define TX3927_DMA_CSR_EXTDN 0x00000010
206 #define TX3927_DMA_CSR_CFERR 0x00000008
207 #define TX3927_DMA_CSR_CHERR 0x00000004
208 #define TX3927_DMA_CSR_DESERR 0x00000002
209 #define TX3927_DMA_CSR_SORERR 0x00000001
214 #define TX3927_IR_INT0 0
215 #define TX3927_IR_INT1 1
216 #define TX3927_IR_INT2 2
217 #define TX3927_IR_INT3 3
218 #define TX3927_IR_INT4 4
219 #define TX3927_IR_INT5 5
220 #define TX3927_IR_SIO0 6
221 #define TX3927_IR_SIO1 7
222 #define TX3927_IR_SIO(ch) (6 + (ch))
223 #define TX3927_IR_DMA 8
224 #define TX3927_IR_PIO 9
225 #define TX3927_IR_PCI 10
226 #define TX3927_IR_TMR(ch) (13 + (ch))
227 #define TX3927_NUM_IR 16
232 /* bits for PCICMD */
233 /* see PCI_COMMAND_XXX in linux/pci.h */
235 /* bits for PCISTAT */
236 /* see PCI_STATUS_XXX in linux/pci.h */
237 #define PCI_STATUS_NEW_CAP 0x0010
240 #define TX3927_PCIC_TC_OF16E 0x00000020
241 #define TX3927_PCIC_TC_IF8E 0x00000010
242 #define TX3927_PCIC_TC_OF8E 0x00000008
244 /* bits for IOBA/MBA */
245 /* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
247 /* bits for PBAPMC */
248 #define TX3927_PCIC_PBAPMC_RPBA 0x00000004
249 #define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
250 #define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
252 /* bits for LBSTAT/LBIM */
253 #define TX3927_PCIC_LBIM_ALL 0x0000003e
255 /* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
256 #define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
259 #define TX3927_PCIC_LBC_IBSE 0x00004000
260 #define TX3927_PCIC_LBC_TIBSE 0x00002000
261 #define TX3927_PCIC_LBC_TMFBSE 0x00001000
262 #define TX3927_PCIC_LBC_HRST 0x00000800
263 #define TX3927_PCIC_LBC_SRST 0x00000400
264 #define TX3927_PCIC_LBC_EPCAD 0x00000200
265 #define TX3927_PCIC_LBC_MSDSE 0x00000100
266 #define TX3927_PCIC_LBC_CRR 0x00000080
267 #define TX3927_PCIC_LBC_ILMDE 0x00000040
268 #define TX3927_PCIC_LBC_ILIDE 0x00000020
270 #define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
271 #define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
276 /* CCFG : Chip Configuration */
277 #define TX3927_CCFG_TLBOFF 0x00020000
278 #define TX3927_CCFG_BEOW 0x00010000
279 #define TX3927_CCFG_WR 0x00008000
280 #define TX3927_CCFG_TOE 0x00004000
281 #define TX3927_CCFG_PCIXARB 0x00002000
282 #define TX3927_CCFG_PCI3 0x00001000
283 #define TX3927_CCFG_PSNP 0x00000800
284 #define TX3927_CCFG_PPRI 0x00000400
285 #define TX3927_CCFG_PLLM 0x00000030
286 #define TX3927_CCFG_ENDIAN 0x00000004
287 #define TX3927_CCFG_HALT 0x00000002
288 #define TX3927_CCFG_ACEHOLD 0x00000001
290 /* PCFG : Pin Configuration */
291 #define TX3927_PCFG_SYSCLKEN 0x08000000
292 #define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
293 #define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
294 #define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
295 #define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
296 #define TX3927_PCFG_SELALL 0x0003ffff
297 #define TX3927_PCFG_SELCS 0x00020000
298 #define TX3927_PCFG_SELDSF 0x00010000
299 #define TX3927_PCFG_SELSIOC_ALL 0x0000c000
300 #define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
301 #define TX3927_PCFG_SELSIO_ALL 0x00003000
302 #define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
303 #define TX3927_PCFG_SELTMR_ALL 0x00000e00
304 #define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
305 #define TX3927_PCFG_SELDONE 0x00000100
306 #define TX3927_PCFG_INTDMA_ALL 0x000000f0
307 #define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
308 #define TX3927_PCFG_SELDMA_ALL 0x0000000f
309 #define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
311 #define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
312 #define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
313 #define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
314 #define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
315 #define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
316 #define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
317 #define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
318 #define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
320 struct pci_controller;
321 void __init tx3927_pcic_setup(struct pci_controller *channel,
322 unsigned long sdram_size, int extarb);
324 #endif /* __ASM_TXX9_TX3927_H */