2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
10 #ifndef _ASM_STACKFRAME_H
11 #define _ASM_STACKFRAME_H
13 #include <linux/config.h>
14 #include <linux/threads.h>
17 #include <asm/asmmacro.h>
18 #include <asm/mipsregs.h>
19 #include <asm/asm-offsets.h>
21 #ifdef CONFIG_MIPS_MT_SMTC
22 #include <asm/mipsmtregs.h>
23 #endif /* CONFIG_MIPS_MT_SMTC */
40 LONG_S $10, PT_R10(sp)
41 LONG_S $11, PT_R11(sp)
43 LONG_S $12, PT_R12(sp)
44 LONG_S $13, PT_R13(sp)
45 LONG_S $14, PT_R14(sp)
46 LONG_S $15, PT_R15(sp)
47 LONG_S $24, PT_R24(sp)
51 LONG_S $16, PT_R16(sp)
52 LONG_S $17, PT_R17(sp)
53 LONG_S $18, PT_R18(sp)
54 LONG_S $19, PT_R19(sp)
55 LONG_S $20, PT_R20(sp)
56 LONG_S $21, PT_R21(sp)
57 LONG_S $22, PT_R22(sp)
58 LONG_S $23, PT_R23(sp)
59 LONG_S $30, PT_R30(sp)
63 .macro get_saved_sp /* SMP variation */
65 #ifdef CONFIG_MIPS_MT_SMTC
71 /* No need to shift down and up to clear bits 0-1 */
78 LONG_L k1, %lo(kernelsp)(k1)
81 #ifdef CONFIG_MIPS_MT_SMTC
85 lui k0, %highest(kernelsp)
87 /* No need to shift down and up to clear bits 0-2 */
90 lui k0, %highest(kernelsp)
92 daddiu k0, %higher(kernelsp)
94 daddiu k0, %hi(kernelsp)
96 #endif /* CONFIG_MIPS_MT_SMTC */
98 LONG_L k1, %lo(kernelsp)(k1)
99 #endif /* CONFIG_64BIT */
102 .macro set_saved_sp stackp temp temp2
104 #ifdef CONFIG_MIPS_MT_SMTC
105 mfc0 \temp, CP0_TCBIND
108 mfc0 \temp, CP0_CONTEXT
113 #ifdef CONFIG_MIPS_MT_SMTC
114 mfc0 \temp, CP0_TCBIND
117 MFC0 \temp, CP0_CONTEXT
121 LONG_S \stackp, kernelsp(\temp)
124 .macro get_saved_sp /* Uniprocessor variation */
126 lui k1, %highest(kernelsp)
127 daddiu k1, %higher(kernelsp)
129 daddiu k1, %hi(kernelsp)
132 lui k1, %hi(kernelsp)
134 LONG_L k1, %lo(kernelsp)(k1)
137 .macro set_saved_sp stackp temp temp2
138 LONG_S \stackp, kernelsp
147 sll k0, 3 /* extract cu0 bit */
152 /* Called from user mode, new stack. */
155 PTR_SUBU sp, k1, PT_SIZE
156 LONG_S k0, PT_R29(sp)
159 * You might think that you don't need to save $0,
160 * but the FPU emulator and gdb remote debug stub
161 * need it to operate correctly
166 LONG_S v1, PT_STATUS(sp)
167 #ifdef CONFIG_MIPS_MT_SMTC
169 * Ideally, these instructions would be shuffled in
170 * to cover the pipeline delay.
173 mfc0 v1, CP0_TCSTATUS
175 LONG_S v1, PT_TCSTATUS(sp)
176 #endif /* CONFIG_MIPS_MT_SMTC */
180 LONG_S v1, PT_CAUSE(sp)
188 LONG_S v1, PT_EPC(sp)
189 LONG_S $25, PT_R25(sp)
190 LONG_S $28, PT_R28(sp)
191 LONG_S $31, PT_R31(sp)
192 ori $28, sp, _THREAD_MASK
193 xori $28, _THREAD_MASK
212 LONG_L $24, PT_LO(sp)
218 LONG_L $24, PT_HI(sp)
219 LONG_L $10, PT_R10(sp)
220 LONG_L $11, PT_R11(sp)
222 LONG_L $12, PT_R12(sp)
223 LONG_L $13, PT_R13(sp)
224 LONG_L $14, PT_R14(sp)
225 LONG_L $15, PT_R15(sp)
226 LONG_L $24, PT_R24(sp)
229 .macro RESTORE_STATIC
230 LONG_L $16, PT_R16(sp)
231 LONG_L $17, PT_R17(sp)
232 LONG_L $18, PT_R18(sp)
233 LONG_L $19, PT_R19(sp)
234 LONG_L $20, PT_R20(sp)
235 LONG_L $21, PT_R21(sp)
236 LONG_L $22, PT_R22(sp)
237 LONG_L $23, PT_R23(sp)
238 LONG_L $30, PT_R30(sp)
241 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
253 LONG_L v0, PT_STATUS(sp)
258 LONG_L $31, PT_R31(sp)
259 LONG_L $28, PT_R28(sp)
260 LONG_L $25, PT_R25(sp)
274 .macro RESTORE_SP_AND_RET
277 LONG_L k0, PT_EPC(sp)
278 LONG_L sp, PT_R29(sp)
286 * For SMTC kernel, global IE should be left set, and interrupts
287 * controlled exclusively via IXMT.
290 #ifdef CONFIG_MIPS_MT_SMTC
291 #define STATMASK 0x1e
293 #define STATMASK 0x1f
299 #ifdef CONFIG_MIPS_MT_SMTC
302 * This may not really be necessary if ints are already
305 mfc0 v0, CP0_TCSTATUS
306 ori v0, TCSTATUS_IXMT
307 mtc0 v0, CP0_TCSTATUS
311 #endif /* CONFIG_MIPS_MT_SMTC */
318 LONG_L v0, PT_STATUS(sp)
323 #ifdef CONFIG_MIPS_MT_SMTC
325 * Only after EXL/ERL have been restored to status can we
326 * restore TCStatus.IXMT.
328 LONG_L v1, PT_TCSTATUS(sp)
330 mfc0 v0, CP0_TCSTATUS
331 andi v1, TCSTATUS_IXMT
332 /* We know that TCStatua.IXMT should be set from above */
333 xori v0, v0, TCSTATUS_IXMT
335 mtc0 v0, CP0_TCSTATUS
337 andi a1, a1, VPECONTROL_TE
342 #endif /* CONFIG_MIPS_MT_SMTC */
343 LONG_L v1, PT_EPC(sp)
345 LONG_L $31, PT_R31(sp)
346 LONG_L $28, PT_R28(sp)
347 LONG_L $25, PT_R25(sp)
361 .macro RESTORE_SP_AND_RET
362 LONG_L sp, PT_R29(sp)
371 LONG_L sp, PT_R29(sp)
382 .macro RESTORE_ALL_AND_RET
391 * Move to kernel mode and disable interrupts.
392 * Set cp0 enable bit as sign that we're running on the kernel stack
395 #if !defined(CONFIG_MIPS_MT_SMTC)
397 li t1, ST0_CU0 | 0x1f
401 #else /* CONFIG_MIPS_MT_SMTC */
403 * For SMTC, we need to set privilege
404 * and disable interrupts only for the
405 * current TC, using the TCStatus register.
408 /* Fortunately CU 0 is in the same place in both registers */
409 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
410 li t1, ST0_CU0 | 0x08001c00
412 /* Clear TKSU, leave IXMT */
414 mtc0 t0, CP0_TCSTATUS
416 /* We need to leave the global IE bit set, but clear EXL...*/
418 ori t0, ST0_EXL | ST0_ERL
419 xori t0, ST0_EXL | ST0_ERL
421 #endif /* CONFIG_MIPS_MT_SMTC */
426 * Move to kernel mode and enable interrupts.
427 * Set cp0 enable bit as sign that we're running on the kernel stack
430 #if !defined(CONFIG_MIPS_MT_SMTC)
432 li t1, ST0_CU0 | 0x1f
436 #else /* CONFIG_MIPS_MT_SMTC */
438 * For SMTC, we need to set privilege
439 * and enable interrupts only for the
440 * current TC, using the TCStatus register.
444 /* Fortunately CU 0 is in the same place in both registers */
445 /* Set TCU0, TKSU (for later inversion) and IXMT */
446 li t1, ST0_CU0 | 0x08001c00
448 /* Clear TKSU *and* IXMT */
450 mtc0 t0, CP0_TCSTATUS
452 /* We need to leave the global IE bit set, but clear EXL...*/
457 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
458 #endif /* CONFIG_MIPS_MT_SMTC */
463 * Just move to kernel mode and leave interrupts as they are.
464 * Set cp0 enable bit as sign that we're running on the kernel stack
467 #ifdef CONFIG_MIPS_MT_SMTC
469 * This gets baroque in SMTC. We want to
470 * protect the non-atomic clearing of EXL
471 * with DMT/EMT, but we don't want to take
472 * an interrupt while DMT is still in effect.
475 /* KMODE gets invoked from both reorder and noreorder code */
479 mfc0 v0, CP0_TCSTATUS
480 andi v1, v0, TCSTATUS_IXMT
481 ori v0, TCSTATUS_IXMT
482 mtc0 v0, CP0_TCSTATUS
486 * We don't know a priori if ra is "live"
492 #endif /* CONFIG_MIPS_MT_SMTC */
494 li t1, ST0_CU0 | 0x1e
498 #ifdef CONFIG_MIPS_MT_SMTC
500 andi v0, v0, VPECONTROL_TE
505 mfc0 v0, CP0_TCSTATUS
506 /* Clear IXMT, then OR in previous value */
507 ori v0, TCSTATUS_IXMT
508 xori v0, TCSTATUS_IXMT
510 mtc0 v0, CP0_TCSTATUS
512 * irq_disable_hazard below should expand to EHB
516 #endif /* CONFIG_MIPS_MT_SMTC */
520 #endif /* _ASM_STACKFRAME_H */