1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * MAC constants and macros File: sb1250_mac.h
6 * This module contains constants and macros for the SB1250's
7 * ethernet controllers.
9 * SB1250 specification level: User's manual 1/02/02
11 * Author: Mitch Lichtenberg
13 *********************************************************************
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 ********************************************************************* */
38 #include "sb1250_defs.h"
40 /* *********************************************************************
41 * Ethernet MAC Registers
42 ********************************************************************* */
45 * MAC Configuration Register (Table 9-13)
52 #define M_MAC_RESERVED0 _SB_MAKEMASK1(0)
53 #define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1)
54 #define M_MAC_RETRY_EN _SB_MAKEMASK1(2)
55 #define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3)
56 #define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4)
57 #define M_MAC_BURST_EN _SB_MAKEMASK1(5)
59 #define S_MAC_TX_PAUSE _SB_MAKE64(6)
60 #define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE)
61 #define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE)
63 #define K_MAC_TX_PAUSE_CNT_512 0
64 #define K_MAC_TX_PAUSE_CNT_1K 1
65 #define K_MAC_TX_PAUSE_CNT_2K 2
66 #define K_MAC_TX_PAUSE_CNT_4K 3
67 #define K_MAC_TX_PAUSE_CNT_8K 4
68 #define K_MAC_TX_PAUSE_CNT_16K 5
69 #define K_MAC_TX_PAUSE_CNT_32K 6
70 #define K_MAC_TX_PAUSE_CNT_64K 7
72 #define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
73 #define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
74 #define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
75 #define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
76 #define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
77 #define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
78 #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
79 #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
81 #define M_MAC_RESERVED1 _SB_MAKEMASK(8,9)
83 #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17)
85 #if SIBYTE_HDR_FEATURE_CHIP(1480)
86 #define M_MAC_TIMESTAMP _SB_MAKEMASK1(18)
88 #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19)
89 #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20)
90 #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21)
91 #define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22)
92 #define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23)
93 #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24)
94 #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25)
96 #define M_MAC_RESERVED3 _SB_MAKEMASK(6,26)
98 #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32)
99 #define M_MAC_HDX_EN _SB_MAKEMASK1(33)
101 #define S_MAC_SPEED_SEL _SB_MAKE64(34)
102 #define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL)
103 #define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL)
104 #define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL)
106 #define K_MAC_SPEED_SEL_10MBPS 0
107 #define K_MAC_SPEED_SEL_100MBPS 1
108 #define K_MAC_SPEED_SEL_1000MBPS 2
109 #define K_MAC_SPEED_SEL_RESERVED 3
111 #define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
112 #define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)
113 #define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
114 #define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
116 #define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36)
117 #define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37)
118 #define M_MAC_FAST_SYNC _SB_MAKEMASK1(38)
119 #define M_MAC_SS_EN _SB_MAKEMASK1(39)
121 #define S_MAC_BYPASS_CFG _SB_MAKE64(40)
122 #define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG)
123 #define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG)
124 #define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG)
126 #define K_MAC_BYPASS_GMII 0
127 #define K_MAC_BYPASS_ENCODED 1
128 #define K_MAC_BYPASS_SOP 2
129 #define K_MAC_BYPASS_EOP 3
131 #define M_MAC_BYPASS_16 _SB_MAKEMASK1(42)
132 #define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43)
134 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
135 #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
136 #endif /* 1250 PASS2 || 112x PASS1 */
138 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
139 #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
140 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
142 #define S_MAC_BYPASS_IFG _SB_MAKE64(46)
143 #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG)
144 #define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG)
145 #define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG)
147 #define K_MAC_FC_CMD_DISABLED 0
148 #define K_MAC_FC_CMD_ENABLED 1
149 #define K_MAC_FC_CMD_ENAB_FALSECARR 2
151 #define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
152 #define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)
153 #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
155 #define M_MAC_FC_SEL _SB_MAKEMASK1(54)
157 #define S_MAC_FC_CMD _SB_MAKE64(55)
158 #define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD)
159 #define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD)
160 #define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD)
162 #define S_MAC_RX_CH_SEL _SB_MAKE64(57)
163 #define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL)
164 #define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL)
165 #define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL)
169 * MAC Enable Registers
170 * Register: MAC_ENABLE_0
171 * Register: MAC_ENABLE_1
172 * Register: MAC_ENABLE_2
175 #define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0)
176 #define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1)
177 #define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4)
178 #define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5)
180 #define M_MAC_PORT_RESET _SB_MAKEMASK1(8)
182 #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
183 #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10)
184 #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11)
185 #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12)
186 #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13)
190 * MAC reset information register (1280/1255)
192 #if SIBYTE_HDR_FEATURE_CHIP(1480)
193 #define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8)
194 #define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16)
195 #define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24)
196 #define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32)
200 * MAC DMA Control Register
201 * Register: MAC_TXD_CTL_0
202 * Register: MAC_TXD_CTL_1
203 * Register: MAC_TXD_CTL_2
206 #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0)
207 #define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0)
208 #define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0)
209 #define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0)
211 #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4)
212 #define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1)
213 #define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1)
214 #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1)
217 * MAC Fifo Threshhold registers (Table 9-14)
218 * Register: MAC_THRSH_CFG_0
219 * Register: MAC_THRSH_CFG_1
220 * Register: MAC_THRSH_CFG_2
223 #define S_MAC_TX_WR_THRSH _SB_MAKE64(0)
224 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
225 /* XXX: Can't enable, as it has the same name as a pass2+ define below. */
226 /* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */
227 #endif /* up to 1250 PASS1 */
228 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
229 #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH)
230 #endif /* 1250 PASS2 || 112x PASS1 */
231 #define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH)
232 #define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH)
234 #define S_MAC_TX_RD_THRSH _SB_MAKE64(8)
235 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
236 /* XXX: Can't enable, as it has the same name as a pass2+ define below. */
237 /* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */
238 #endif /* up to 1250 PASS1 */
239 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
240 #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH)
241 #endif /* 1250 PASS2 || 112x PASS1 */
242 #define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH)
243 #define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH)
245 #define S_MAC_TX_RL_THRSH _SB_MAKE64(16)
246 #define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH)
247 #define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH)
248 #define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH)
250 #define S_MAC_RX_PL_THRSH _SB_MAKE64(24)
251 #define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH)
252 #define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH)
253 #define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH)
255 #define S_MAC_RX_RD_THRSH _SB_MAKE64(32)
256 #define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH)
257 #define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH)
258 #define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH)
260 #define S_MAC_RX_RL_THRSH _SB_MAKE64(40)
261 #define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH)
262 #define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH)
263 #define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH)
265 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
266 #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
267 #define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH)
268 #define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH)
269 #define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH)
270 #endif /* 1250 PASS2 || 112x PASS1 */
273 * MAC Frame Configuration Registers (Table 9-15)
274 * Register: MAC_FRAME_CFG_0
275 * Register: MAC_FRAME_CFG_1
276 * Register: MAC_FRAME_CFG_2
279 /* XXXCGD: ??? Unused in pass2? */
280 #define S_MAC_IFG_RX _SB_MAKE64(0)
281 #define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX)
282 #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX)
283 #define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX)
285 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
286 #define S_MAC_PRE_LEN _SB_MAKE64(0)
287 #define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN)
288 #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN)
289 #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN)
290 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
292 #define S_MAC_IFG_TX _SB_MAKE64(6)
293 #define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX)
294 #define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX)
295 #define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX)
297 #define S_MAC_IFG_THRSH _SB_MAKE64(12)
298 #define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH)
299 #define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH)
300 #define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH)
302 #define S_MAC_BACKOFF_SEL _SB_MAKE64(18)
303 #define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL)
304 #define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL)
305 #define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL)
307 #define S_MAC_LFSR_SEED _SB_MAKE64(22)
308 #define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED)
309 #define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED)
310 #define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED)
312 #define S_MAC_SLOT_SIZE _SB_MAKE64(30)
313 #define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE)
314 #define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE)
315 #define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE)
317 #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40)
318 #define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ)
319 #define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ)
320 #define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ)
322 #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48)
323 #define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ)
324 #define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ)
325 #define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ)
328 * These constants are used to configure the fields within the Frame
329 * Configuration Register.
332 #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */
333 #define K_MAC_IFG_RX_100 _SB_MAKE64(0)
334 #define K_MAC_IFG_RX_1000 _SB_MAKE64(0)
336 #define K_MAC_IFG_TX_10 _SB_MAKE64(20)
337 #define K_MAC_IFG_TX_100 _SB_MAKE64(20)
338 #define K_MAC_IFG_TX_1000 _SB_MAKE64(8)
340 #define K_MAC_IFG_THRSH_10 _SB_MAKE64(4)
341 #define K_MAC_IFG_THRSH_100 _SB_MAKE64(4)
342 #define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0)
344 #define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0)
345 #define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0)
346 #define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0)
348 #define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10)
349 #define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100)
350 #define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
352 #define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10)
353 #define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100)
354 #define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
356 #define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10)
357 #define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100)
358 #define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000)
360 #define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10)
361 #define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
362 #define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
364 #define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9)
365 #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64)
366 #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518)
367 #define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216)
369 #define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
370 #define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
371 #define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
372 #define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
375 * MAC VLAN Tag Registers (Table 9-16)
376 * Register: MAC_VLANTAG_0
377 * Register: MAC_VLANTAG_1
378 * Register: MAC_VLANTAG_2
381 #define S_MAC_VLAN_TAG _SB_MAKE64(0)
382 #define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG)
383 #define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG)
384 #define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG)
386 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
387 #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32)
388 #define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET)
389 #define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET)
390 #define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET)
392 #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40)
393 #define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET)
394 #define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET)
395 #define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET)
397 #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48)
398 #endif /* 1250 PASS3 || 112x PASS1 */
401 * MAC Status Registers (Table 9-17)
402 * Also used for the MAC Interrupt Mask Register (Table 9-18)
403 * Register: MAC_STATUS_0
404 * Register: MAC_STATUS_1
405 * Register: MAC_STATUS_2
406 * Register: MAC_INT_MASK_0
407 * Register: MAC_INT_MASK_1
408 * Register: MAC_INT_MASK_2
412 * Use these constants to shift the appropriate channel
413 * into the CH0 position so the same tests can be used
417 #define S_MAC_RX_CH0 _SB_MAKE64(0)
418 #define S_MAC_RX_CH1 _SB_MAKE64(8)
419 #define S_MAC_TX_CH0 _SB_MAKE64(16)
420 #define S_MAC_TX_CH1 _SB_MAKE64(24)
422 #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */
423 #define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */
426 * These are the same as RX channel 0. The idea here
427 * is that you'll use one of the "S_" things above
428 * and pass just the six bits to a DMA-channel-specific ISR
430 #define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0)
431 #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0)
432 #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1)
433 #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2)
434 #define M_MAC_INT_HWM _SB_MAKEMASK1(3)
435 #define M_MAC_INT_LWM _SB_MAKEMASK1(4)
436 #define M_MAC_INT_DSCR _SB_MAKEMASK1(5)
437 #define M_MAC_INT_ERR _SB_MAKEMASK1(6)
438 #define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */
439 #define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */
442 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
443 * also DMA_TX/DMA_RX in sb_regs.h).
445 #define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
447 #define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx))
448 #define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx))
449 #define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx))
450 #define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx))
451 #define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))
452 #define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))
453 #define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx))
454 #define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx))
455 #define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx))
456 #define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx))
457 #define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40)
460 #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40)
461 #define M_MAC_RX_OVRFL _SB_MAKEMASK1(41)
462 #define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42)
463 #define M_MAC_TX_OVRFL _SB_MAKEMASK1(43)
464 #define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44)
465 #define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45)
466 #define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46)
467 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
468 #define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */
469 #endif /* 1250 PASS2 || 112x PASS1 */
471 #define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
472 #define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR)
473 #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)
474 #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)
476 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
477 #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
478 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
481 * MAC Fifo Pointer Registers (Table 9-19) [Debug register]
482 * Register: MAC_FIFO_PTRS_0
483 * Register: MAC_FIFO_PTRS_1
484 * Register: MAC_FIFO_PTRS_2
487 #define S_MAC_TX_WRPTR _SB_MAKE64(0)
488 #define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR)
489 #define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR)
490 #define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR)
492 #define S_MAC_TX_RDPTR _SB_MAKE64(8)
493 #define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR)
494 #define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR)
495 #define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR)
497 #define S_MAC_RX_WRPTR _SB_MAKE64(16)
498 #define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR)
499 #define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR)
500 #define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR)
502 #define S_MAC_RX_RDPTR _SB_MAKE64(24)
503 #define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR)
504 #define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR)
505 #define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR)
508 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register]
509 * Register: MAC_EOPCNT_0
510 * Register: MAC_EOPCNT_1
511 * Register: MAC_EOPCNT_2
514 #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0)
515 #define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER)
516 #define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER)
517 #define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER)
519 #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8)
520 #define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER)
521 #define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER)
522 #define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER)
525 * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
526 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
527 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
528 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
534 * MAC Receive Address Filter Mask Registers
535 * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1
536 * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1
537 * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1
543 * MAC Recieve Address Filter Hash Match Registers (Table 9-22)
544 * Registers: MAC_HASH0_0 through MAC_HASH7_0
545 * Registers: MAC_HASH0_1 through MAC_HASH7_1
546 * Registers: MAC_HASH0_2 through MAC_HASH7_2
552 * MAC Transmit Source Address Registers (Table 9-23)
553 * Register: MAC_ETHERNET_ADDR_0
554 * Register: MAC_ETHERNET_ADDR_1
555 * Register: MAC_ETHERNET_ADDR_2
561 * MAC Packet Type Configuration Register
562 * Register: MAC_TYPE_CFG_0
563 * Register: MAC_TYPE_CFG_1
564 * Register: MAC_TYPE_CFG_2
567 #define S_TYPECFG_TYPESIZE _SB_MAKE64(16)
569 #define S_TYPECFG_TYPE0 _SB_MAKE64(0)
570 #define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0)
571 #define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0)
572 #define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0)
574 #define S_TYPECFG_TYPE1 _SB_MAKE64(0)
575 #define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1)
576 #define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1)
577 #define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1)
579 #define S_TYPECFG_TYPE2 _SB_MAKE64(0)
580 #define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2)
581 #define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2)
582 #define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2)
584 #define S_TYPECFG_TYPE3 _SB_MAKE64(0)
585 #define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3)
586 #define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3)
587 #define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3)
590 * MAC Receive Address Filter Control Registers (Table 9-24)
591 * Register: MAC_ADFILTER_CFG_0
592 * Register: MAC_ADFILTER_CFG_1
593 * Register: MAC_ADFILTER_CFG_2
596 #define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0)
597 #define M_MAC_UCAST_EN _SB_MAKEMASK1(1)
598 #define M_MAC_UCAST_INV _SB_MAKEMASK1(2)
599 #define M_MAC_MCAST_EN _SB_MAKEMASK1(3)
600 #define M_MAC_MCAST_INV _SB_MAKEMASK1(4)
601 #define M_MAC_BCAST_EN _SB_MAKEMASK1(5)
602 #define M_MAC_DIRECT_INV _SB_MAKEMASK1(6)
603 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
604 #define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7)
605 #endif /* 1250 PASS2 || 112x PASS1 */
607 #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
608 #define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET)
609 #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)
610 #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)
612 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
613 #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
614 #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)
615 #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)
616 #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET)
618 #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24)
619 #define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET)
620 #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET)
621 #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET)
623 #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32)
624 #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33)
626 #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34)
627 #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)
628 #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)
629 #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)
630 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
633 * MAC Receive Channel Select Registers (Table 9-25)
639 * MAC MII Management Interface Registers (Table 9-26)
640 * Register: MAC_MDIO_0
641 * Register: MAC_MDIO_1
642 * Register: MAC_MDIO_2
646 #define S_MAC_MDIO_DIR 1
647 #define S_MAC_MDIO_OUT 2
649 #define S_MAC_MDIO_IN 4
651 #define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC)
652 #define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR)
653 #define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR)
654 #define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT)
655 #define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC)
656 #define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN)