1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * DMA definitions File: sb1250_dma.h
6 * This module contains constants and macros useful for
7 * programming the SB1250's DMA controllers, both the data mover
8 * and the Ethernet DMA.
10 * SB1250 specification level: User's manual 1/02/02
12 * Author: Mitch Lichtenberg
14 *********************************************************************
16 * Copyright 2000,2001,2002,2003
17 * Broadcom Corporation. All rights reserved.
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 ********************************************************************* */
40 #include "sb1250_defs.h"
42 /* *********************************************************************
44 ********************************************************************* */
47 * Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
48 * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
49 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
50 * Registers: DMA_CONFIG0_SER_x_RX
51 * Registers: DMA_CONFIG0_SER_x_TX
55 #define M_DMA_DROP _SB_MAKEMASK1(0)
57 #define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)
58 #define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
60 #define S_DMA_DESC_TYPE _SB_MAKE64(1)
61 #define M_DMA_DESC_TYPE _SB_MAKEMASK(2,S_DMA_DESC_TYPE)
62 #define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
63 #define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
65 #define K_DMA_DESC_TYPE_RING_AL 0
66 #define K_DMA_DESC_TYPE_CHAIN_AL 1
68 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
69 #define K_DMA_DESC_TYPE_RING_UAL_WI 2
70 #define K_DMA_DESC_TYPE_RING_UAL_RMW 3
71 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
73 #define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
74 #define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
75 #define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)
76 #define M_DMA_TBX_EN _SB_MAKEMASK1(6)
77 #define M_DMA_TDX_EN _SB_MAKEMASK1(7)
79 #define S_DMA_INT_PKTCNT _SB_MAKE64(8)
80 #define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT)
81 #define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT)
82 #define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT)
84 #define S_DMA_RINGSZ _SB_MAKE64(16)
85 #define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ)
86 #define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ)
87 #define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ)
89 #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
90 #define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK)
91 #define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK)
92 #define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK)
94 #define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
95 #define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK)
96 #define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK)
97 #define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)
100 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
101 * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
102 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
103 * Registers: DMA_CONFIG1_SER_x_RX
104 * Registers: DMA_CONFIG1_SER_x_TX
107 #define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0)
108 #define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1)
109 #define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2)
110 #define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3)
111 #define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
112 #define M_DMA_L2CA _SB_MAKEMASK1(5)
114 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
115 #define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
116 #define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
117 #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
118 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
120 #define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
122 #define S_DMA_HDR_SIZE _SB_MAKE64(21)
123 #define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE)
124 #define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE)
125 #define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE)
127 #define M_DMA_MBZ2 _SB_MAKEMASK(5,32)
129 #define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
130 #define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE)
131 #define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE)
132 #define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE)
134 #define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
135 #define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT)
136 #define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT)
137 #define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT)
140 * Ethernet and Serial DMA Descriptor base address (Table 7-6)
143 #define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0)
147 * ASIC Mode Base Address (Table 7-7)
150 #define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0)
153 * DMA Descriptor Count Registers (Table 7-8)
160 * Current Descriptor Address Register (Table 7-11)
163 #define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
164 #define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)
165 #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
166 #define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
168 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
169 #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
170 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
173 * Receive Packet Drop Registers
175 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
176 #define S_DMA_OODLOST_RX _SB_MAKE64(0)
177 #define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
178 #define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
180 #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
181 #define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
182 #define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
183 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
185 /* *********************************************************************
187 ********************************************************************* */
190 * Descriptor doubleword "A" (Table 7-12)
193 #define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
194 #define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)
195 #define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET)
196 #define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET)
198 /* Note: Don't shift the address over, just mask it with the mask below */
199 #define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
200 #define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR)
202 #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
204 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
205 #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
206 #define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
207 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
209 #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
210 #define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
211 #define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
212 #define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
214 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
215 #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
216 #define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
217 #define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
218 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
220 #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
221 #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
223 #define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
224 #define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS)
225 #define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS)
226 #define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS)
229 * Descriptor doubleword "B" (Table 7-13)
233 #define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
234 #define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS)
235 #define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
236 #define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
238 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
239 #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
240 #define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
241 #define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
242 #define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
243 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
245 #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
247 /* Note: Don't shift the address over, just mask it with the mask below */
248 #define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
249 #define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR)
251 #define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
252 #define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE)
253 #define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE)
254 #define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE)
256 #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
258 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
259 #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
260 #define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
261 #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
262 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
263 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
265 #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
266 #define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
267 #define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)
268 #define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)
271 * from pass2 some bits in dscr_b are also used for rx status
273 #define S_DMA_DSCRB_STATUS _SB_MAKE64(0)
274 #define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS)
275 #define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
276 #define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
279 * Ethernet Descriptor Status Bits (Table 7-15)
282 #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
283 #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
285 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
286 /* Note: This bit is in the DSCR_B options field */
287 #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
288 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
290 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
291 /* Note: These bits are in the DSCR_B options field */
292 #define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
293 #define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
294 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
296 #define S_DMA_ETHRX_RXCH 53
297 #define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
298 #define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH)
299 #define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH)
301 #define S_DMA_ETHRX_PKTTYPE 55
302 #define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE)
303 #define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE)
304 #define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE)
306 #define K_DMA_ETHRX_PKTTYPE_IPV4 0
307 #define K_DMA_ETHRX_PKTTYPE_ARPV4 1
308 #define K_DMA_ETHRX_PKTTYPE_802 2
309 #define K_DMA_ETHRX_PKTTYPE_OTHER 3
310 #define K_DMA_ETHRX_PKTTYPE_USER0 4
311 #define K_DMA_ETHRX_PKTTYPE_USER1 5
312 #define K_DMA_ETHRX_PKTTYPE_USER2 6
313 #define K_DMA_ETHRX_PKTTYPE_USER3 7
315 #define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58)
316 #define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59)
317 #define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60)
318 #define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61)
319 #define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62)
320 #define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63)
323 * Ethernet Transmit Status Bits (Table 7-16)
326 #define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
329 * Ethernet Transmit Options (Table 7-17)
332 #define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00)
333 #define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01)
334 #define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02)
335 #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
336 #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
337 #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
338 #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
339 #define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07)
340 #define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08)
341 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
342 #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
343 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
344 #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
345 #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
346 #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
347 #define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F)
350 * Serial Receive Options (Table 7-18)
352 #define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56)
353 #define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57)
354 #define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58)
355 #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
356 #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
357 #define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61)
358 #define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62)
359 #define M_DMA_SERRX_SOP _SB_MAKEMASK1(63)
362 * Serial Transmit Status Bits (Table 7-20)
365 #define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63)
368 * Serial Transmit Options (Table 7-21)
371 #define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0)
372 #define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1)
373 #define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2)
374 #define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3)
377 /* *********************************************************************
378 * Data Mover Registers
379 ********************************************************************* */
382 * Data Mover Descriptor Base Address Register (Table 7-22)
383 * Register: DM_DSCR_BASE_0
384 * Register: DM_DSCR_BASE_1
385 * Register: DM_DSCR_BASE_2
386 * Register: DM_DSCR_BASE_3
389 #define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0)
391 /* Note: Just mask the base address and then OR it in. */
392 #define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4)
393 #define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR)
395 #define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
396 #define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ)
397 #define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ)
398 #define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ)
400 #define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
401 #define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY)
402 #define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY)
403 #define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY)
405 #define K_DM_DSCR_BASE_PRIORITY_1 0
406 #define K_DM_DSCR_BASE_PRIORITY_2 1
407 #define K_DM_DSCR_BASE_PRIORITY_4 2
408 #define K_DM_DSCR_BASE_PRIORITY_8 3
409 #define K_DM_DSCR_BASE_PRIORITY_16 4
411 #define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59)
412 #define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60)
413 #define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */
414 #define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */
415 #define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
416 #define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
419 * Data Mover Descriptor Count Register (Table 7-25)
425 * Data Mover Current Descriptor Address (Table 7-24)
426 * Register: DM_CUR_DSCR_ADDR_0
427 * Register: DM_CUR_DSCR_ADDR_1
428 * Register: DM_CUR_DSCR_ADDR_2
429 * Register: DM_CUR_DSCR_ADDR_3
432 #define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
433 #define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR)
435 #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
436 #define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT)
437 #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT)
438 #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\
439 M_DM_CUR_DSCR_DSCR_COUNT)
442 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
444 * Data Mover Channel Partial Result Registers
445 * Register: DM_PARTIAL_0
446 * Register: DM_PARTIAL_1
447 * Register: DM_PARTIAL_2
448 * Register: DM_PARTIAL_3
450 #define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0)
451 #define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL)
452 #define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL)
453 #define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\
454 M_DM_PARTIAL_CRC_PARTIAL)
456 #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32)
457 #define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL)
458 #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL)
459 #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\
460 M_DM_PARTIAL_TCPCS_PARTIAL)
462 #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
463 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
466 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
468 * Data Mover CRC Definition Registers
469 * Register: CRC_DEF_0
470 * Register: CRC_DEF_1
472 #define S_CRC_DEF_CRC_INIT _SB_MAKE64(0)
473 #define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT)
474 #define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT)
475 #define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\
478 #define S_CRC_DEF_CRC_POLY _SB_MAKE64(32)
479 #define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY)
480 #define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
481 #define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
483 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
486 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
488 * Data Mover CRC/Checksum Definition Registers
489 * Register: CTCP_DEF_0
490 * Register: CTCP_DEF_1
492 #define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0)
493 #define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR)
494 #define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR)
495 #define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\
498 #define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32)
499 #define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT)
500 #define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT)
501 #define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\
502 M_CTCP_DEF_TCPCS_INIT)
504 #define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48)
505 #define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH)
506 #define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH)
507 #define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\
508 M_CTCP_DEF_CRC_WIDTH)
510 #define K_CTCP_DEF_CRC_WIDTH_4 0
511 #define K_CTCP_DEF_CRC_WIDTH_2 1
512 #define K_CTCP_DEF_CRC_WIDTH_1 2
514 #define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
515 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
519 * Data Mover Descriptor Doubleword "A" (Table 7-26)
522 #define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
523 #define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR)
525 #define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
526 #define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
527 #define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42)
528 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
529 #define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43)
530 #endif /* up to 1250 PASS1 */
532 #define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
533 #define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST)
534 #define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST)
535 #define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST)
537 #define K_DM_DSCRA_DIR_DEST_INCR 0
538 #define K_DM_DSCRA_DIR_DEST_DECR 1
539 #define K_DM_DSCRA_DIR_DEST_CONST 2
541 #define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST)
542 #define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST)
543 #define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST)
545 #define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
546 #define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC)
547 #define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC)
548 #define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC)
550 #define K_DM_DSCRA_DIR_SRC_INCR 0
551 #define K_DM_DSCRA_DIR_SRC_DECR 1
552 #define K_DM_DSCRA_DIR_SRC_CONST 2
554 #define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC)
555 #define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC)
556 #define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC)
559 #define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
560 #define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49)
561 #define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
562 #define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
564 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
565 #define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
566 #define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
567 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
569 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
570 #define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
571 #define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
572 #define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
573 #define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57)
574 #define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58)
575 #define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
576 #define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
577 #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
578 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
580 #define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61)
583 * Data Mover Descriptor Doubleword "B" (Table 7-25)
586 #define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
587 #define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR)
589 #define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
590 #define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH)
591 #define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH)
592 #define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH)