2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/config.h>
17 #include <linux/linkage.h>
18 #include <asm/hazards.h>
21 * The following macros are especially useful for __asm__
28 #define STR(x) __STR(x)
37 #define _ULCAST_ (unsigned long)
41 * Coprocessor 0 register names
45 #define CP0_ENTRYLO0 $2
46 #define CP0_ENTRYLO1 $3
48 #define CP0_CONTEXT $4
49 #define CP0_PAGEMASK $5
52 #define CP0_BADVADDR $8
54 #define CP0_ENTRYHI $10
55 #define CP0_COMPARE $11
56 #define CP0_STATUS $12
60 #define CP0_CONFIG $16
61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22
69 #define CP0_PERFORMANCE $25
71 #define CP0_CACHEERR $27
74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31
78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them
88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19
92 * Coprocessor 0 Set 1 register names
94 #define CP0_S1_DERRADDR0 $26
95 #define CP0_S1_DERRADDR1 $27
96 #define CP0_S1_INTCONTROL $20
101 #define CP0_TX39_CACHE $7
104 * Coprocessor 1 (FPU) register names
106 #define CP1_REVISION $0
107 #define CP1_STATUS $31
110 * FPU Status Register Values
113 * Status Register Values
116 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
117 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
118 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
119 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
120 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
121 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
122 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
123 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
124 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
125 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
128 * X the exception cause indicator
129 * E the exception enable
130 * S the sticky/flag bit
132 #define FPU_CSR_ALL_X 0x0003f000
133 #define FPU_CSR_UNI_X 0x00020000
134 #define FPU_CSR_INV_X 0x00010000
135 #define FPU_CSR_DIV_X 0x00008000
136 #define FPU_CSR_OVF_X 0x00004000
137 #define FPU_CSR_UDF_X 0x00002000
138 #define FPU_CSR_INE_X 0x00001000
140 #define FPU_CSR_ALL_E 0x00000f80
141 #define FPU_CSR_INV_E 0x00000800
142 #define FPU_CSR_DIV_E 0x00000400
143 #define FPU_CSR_OVF_E 0x00000200
144 #define FPU_CSR_UDF_E 0x00000100
145 #define FPU_CSR_INE_E 0x00000080
147 #define FPU_CSR_ALL_S 0x0000007c
148 #define FPU_CSR_INV_S 0x00000040
149 #define FPU_CSR_DIV_S 0x00000020
150 #define FPU_CSR_OVF_S 0x00000010
151 #define FPU_CSR_UDF_S 0x00000008
152 #define FPU_CSR_INE_S 0x00000004
155 #define FPU_CSR_RN 0x0 /* nearest */
156 #define FPU_CSR_RZ 0x1 /* towards zero */
157 #define FPU_CSR_RU 0x2 /* towards +Infinity */
158 #define FPU_CSR_RD 0x3 /* towards -Infinity */
162 * Values for PageMask register
164 #ifdef CONFIG_CPU_VR41XX
166 /* Why doesn't stupidity hurt ... */
168 #define PM_1K 0x00000000
169 #define PM_4K 0x00001800
170 #define PM_16K 0x00007800
171 #define PM_64K 0x0001f800
172 #define PM_256K 0x0007f800
176 #define PM_4K 0x00000000
177 #define PM_16K 0x00006000
178 #define PM_64K 0x0001e000
179 #define PM_256K 0x0007e000
180 #define PM_1M 0x001fe000
181 #define PM_4M 0x007fe000
182 #define PM_16M 0x01ffe000
183 #define PM_64M 0x07ffe000
184 #define PM_256M 0x1fffe000
189 * Default page size for a given kernel configuration
191 #ifdef CONFIG_PAGE_SIZE_4KB
192 #define PM_DEFAULT_MASK PM_4K
193 #elif defined(CONFIG_PAGE_SIZE_16KB)
194 #define PM_DEFAULT_MASK PM_16K
195 #elif defined(CONFIG_PAGE_SIZE_64KB)
196 #define PM_DEFAULT_MASK PM_64K
198 #error Bad page size configuration!
203 * Values used for computation of new tlb entries
216 * R4x00 interrupt enable / cause bits
218 #define IE_SW0 (_ULCAST_(1) << 8)
219 #define IE_SW1 (_ULCAST_(1) << 9)
220 #define IE_IRQ0 (_ULCAST_(1) << 10)
221 #define IE_IRQ1 (_ULCAST_(1) << 11)
222 #define IE_IRQ2 (_ULCAST_(1) << 12)
223 #define IE_IRQ3 (_ULCAST_(1) << 13)
224 #define IE_IRQ4 (_ULCAST_(1) << 14)
225 #define IE_IRQ5 (_ULCAST_(1) << 15)
228 * R4x00 interrupt cause bits
230 #define C_SW0 (_ULCAST_(1) << 8)
231 #define C_SW1 (_ULCAST_(1) << 9)
232 #define C_IRQ0 (_ULCAST_(1) << 10)
233 #define C_IRQ1 (_ULCAST_(1) << 11)
234 #define C_IRQ2 (_ULCAST_(1) << 12)
235 #define C_IRQ3 (_ULCAST_(1) << 13)
236 #define C_IRQ4 (_ULCAST_(1) << 14)
237 #define C_IRQ5 (_ULCAST_(1) << 15)
240 * Bitfields in the R4xx0 cp0 status register
242 #define ST0_IE 0x00000001
243 #define ST0_EXL 0x00000002
244 #define ST0_ERL 0x00000004
245 #define ST0_KSU 0x00000018
246 # define KSU_USER 0x00000010
247 # define KSU_SUPERVISOR 0x00000008
248 # define KSU_KERNEL 0x00000000
249 #define ST0_UX 0x00000020
250 #define ST0_SX 0x00000040
251 #define ST0_KX 0x00000080
252 #define ST0_DE 0x00010000
253 #define ST0_CE 0x00020000
256 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
257 * cacheops in userspace. This bit exists only on RM7000 and RM9000
260 #define ST0_CO 0x08000000
263 * Bitfields in the R[23]000 cp0 status register.
265 #define ST0_IEC 0x00000001
266 #define ST0_KUC 0x00000002
267 #define ST0_IEP 0x00000004
268 #define ST0_KUP 0x00000008
269 #define ST0_IEO 0x00000010
270 #define ST0_KUO 0x00000020
271 /* bits 6 & 7 are reserved on R[23]000 */
272 #define ST0_ISC 0x00010000
273 #define ST0_SWC 0x00020000
274 #define ST0_CM 0x00080000
277 * Bits specific to the R4640/R4650
279 #define ST0_UM (_ULCAST_(1) << 4)
280 #define ST0_IL (_ULCAST_(1) << 23)
281 #define ST0_DL (_ULCAST_(1) << 24)
284 * Bitfields in the TX39 family CP0 Configuration Register 3
286 #define TX39_CONF_ICS_SHIFT 19
287 #define TX39_CONF_ICS_MASK 0x00380000
288 #define TX39_CONF_ICS_1KB 0x00000000
289 #define TX39_CONF_ICS_2KB 0x00080000
290 #define TX39_CONF_ICS_4KB 0x00100000
291 #define TX39_CONF_ICS_8KB 0x00180000
292 #define TX39_CONF_ICS_16KB 0x00200000
294 #define TX39_CONF_DCS_SHIFT 16
295 #define TX39_CONF_DCS_MASK 0x00070000
296 #define TX39_CONF_DCS_1KB 0x00000000
297 #define TX39_CONF_DCS_2KB 0x00010000
298 #define TX39_CONF_DCS_4KB 0x00020000
299 #define TX39_CONF_DCS_8KB 0x00030000
300 #define TX39_CONF_DCS_16KB 0x00040000
302 #define TX39_CONF_CWFON 0x00004000
303 #define TX39_CONF_WBON 0x00002000
304 #define TX39_CONF_RF_SHIFT 10
305 #define TX39_CONF_RF_MASK 0x00000c00
306 #define TX39_CONF_DOZE 0x00000200
307 #define TX39_CONF_HALT 0x00000100
308 #define TX39_CONF_LOCK 0x00000080
309 #define TX39_CONF_ICE 0x00000020
310 #define TX39_CONF_DCE 0x00000010
311 #define TX39_CONF_IRSIZE_SHIFT 2
312 #define TX39_CONF_IRSIZE_MASK 0x0000000c
313 #define TX39_CONF_DRSIZE_SHIFT 0
314 #define TX39_CONF_DRSIZE_MASK 0x00000003
317 * Status register bits available in all MIPS CPUs.
319 #define ST0_IM 0x0000ff00
320 #define STATUSB_IP0 8
321 #define STATUSF_IP0 (_ULCAST_(1) << 8)
322 #define STATUSB_IP1 9
323 #define STATUSF_IP1 (_ULCAST_(1) << 9)
324 #define STATUSB_IP2 10
325 #define STATUSF_IP2 (_ULCAST_(1) << 10)
326 #define STATUSB_IP3 11
327 #define STATUSF_IP3 (_ULCAST_(1) << 11)
328 #define STATUSB_IP4 12
329 #define STATUSF_IP4 (_ULCAST_(1) << 12)
330 #define STATUSB_IP5 13
331 #define STATUSF_IP5 (_ULCAST_(1) << 13)
332 #define STATUSB_IP6 14
333 #define STATUSF_IP6 (_ULCAST_(1) << 14)
334 #define STATUSB_IP7 15
335 #define STATUSF_IP7 (_ULCAST_(1) << 15)
336 #define STATUSB_IP8 0
337 #define STATUSF_IP8 (_ULCAST_(1) << 0)
338 #define STATUSB_IP9 1
339 #define STATUSF_IP9 (_ULCAST_(1) << 1)
340 #define STATUSB_IP10 2
341 #define STATUSF_IP10 (_ULCAST_(1) << 2)
342 #define STATUSB_IP11 3
343 #define STATUSF_IP11 (_ULCAST_(1) << 3)
344 #define STATUSB_IP12 4
345 #define STATUSF_IP12 (_ULCAST_(1) << 4)
346 #define STATUSB_IP13 5
347 #define STATUSF_IP13 (_ULCAST_(1) << 5)
348 #define STATUSB_IP14 6
349 #define STATUSF_IP14 (_ULCAST_(1) << 6)
350 #define STATUSB_IP15 7
351 #define STATUSF_IP15 (_ULCAST_(1) << 7)
352 #define ST0_CH 0x00040000
353 #define ST0_SR 0x00100000
354 #define ST0_TS 0x00200000
355 #define ST0_BEV 0x00400000
356 #define ST0_RE 0x02000000
357 #define ST0_FR 0x04000000
358 #define ST0_CU 0xf0000000
359 #define ST0_CU0 0x10000000
360 #define ST0_CU1 0x20000000
361 #define ST0_CU2 0x40000000
362 #define ST0_CU3 0x80000000
363 #define ST0_XX 0x80000000 /* MIPS IV naming */
366 * Bitfields and bit numbers in the coprocessor 0 cause register.
368 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
370 #define CAUSEB_EXCCODE 2
371 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
373 #define CAUSEF_IP (_ULCAST_(255) << 8)
375 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
377 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
378 #define CAUSEB_IP2 10
379 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
380 #define CAUSEB_IP3 11
381 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
382 #define CAUSEB_IP4 12
383 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
384 #define CAUSEB_IP5 13
385 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
386 #define CAUSEB_IP6 14
387 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
388 #define CAUSEB_IP7 15
389 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
391 #define CAUSEF_IV (_ULCAST_(1) << 23)
393 #define CAUSEF_CE (_ULCAST_(3) << 28)
395 #define CAUSEF_BD (_ULCAST_(1) << 31)
398 * Bits in the coprocessor 0 config register.
401 #define CONF_CM_CACHABLE_NO_WA 0
402 #define CONF_CM_CACHABLE_WA 1
403 #define CONF_CM_UNCACHED 2
404 #define CONF_CM_CACHABLE_NONCOHERENT 3
405 #define CONF_CM_CACHABLE_CE 4
406 #define CONF_CM_CACHABLE_COW 5
407 #define CONF_CM_CACHABLE_CUW 6
408 #define CONF_CM_CACHABLE_ACCELERATED 7
409 #define CONF_CM_CMASK 7
410 #define CONF_BE (_ULCAST_(1) << 15)
412 /* Bits common to various processors. */
413 #define CONF_CU (_ULCAST_(1) << 3)
414 #define CONF_DB (_ULCAST_(1) << 4)
415 #define CONF_IB (_ULCAST_(1) << 5)
416 #define CONF_DC (_ULCAST_(7) << 6)
417 #define CONF_IC (_ULCAST_(7) << 9)
418 #define CONF_EB (_ULCAST_(1) << 13)
419 #define CONF_EM (_ULCAST_(1) << 14)
420 #define CONF_SM (_ULCAST_(1) << 16)
421 #define CONF_SC (_ULCAST_(1) << 17)
422 #define CONF_EW (_ULCAST_(3) << 18)
423 #define CONF_EP (_ULCAST_(15)<< 24)
424 #define CONF_EC (_ULCAST_(7) << 28)
425 #define CONF_CM (_ULCAST_(1) << 31)
427 /* Bits specific to the R4xx0. */
428 #define R4K_CONF_SW (_ULCAST_(1) << 20)
429 #define R4K_CONF_SS (_ULCAST_(1) << 21)
430 #define R4K_CONF_SB (_ULCAST_(3) << 22)
432 /* Bits specific to the R5000. */
433 #define R5K_CONF_SE (_ULCAST_(1) << 12)
434 #define R5K_CONF_SS (_ULCAST_(3) << 20)
436 /* Bits specific to the RM7000. */
437 #define R7K_CONF_SE (_ULCAST_(1) << 3)
439 /* Bits specific to the R10000. */
440 #define R10K_CONF_DN (_ULCAST_(3) << 3)
441 #define R10K_CONF_CT (_ULCAST_(1) << 5)
442 #define R10K_CONF_PE (_ULCAST_(1) << 6)
443 #define R10K_CONF_PM (_ULCAST_(3) << 7)
444 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
445 #define R10K_CONF_SB (_ULCAST_(1) << 13)
446 #define R10K_CONF_SK (_ULCAST_(1) << 14)
447 #define R10K_CONF_SS (_ULCAST_(7) << 16)
448 #define R10K_CONF_SC (_ULCAST_(7) << 19)
449 #define R10K_CONF_DC (_ULCAST_(7) << 26)
450 #define R10K_CONF_IC (_ULCAST_(7) << 29)
452 /* Bits specific to the VR41xx. */
453 #define VR41_CONF_CS (_ULCAST_(1) << 12)
454 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
455 #define VR41_CONF_AD (_ULCAST_(1) << 23)
457 /* Bits specific to the R30xx. */
458 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
459 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
460 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
461 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
462 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
463 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
464 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
465 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
466 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
468 /* Bits specific to the TX49. */
469 #define TX49_CONF_DC (_ULCAST_(1) << 16)
470 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
471 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
472 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
474 /* Bits specific to the MIPS32/64 PRA. */
475 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
476 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
477 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
478 #define MIPS_CONF_M (_ULCAST_(1) << 31)
481 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
483 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
484 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
485 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
486 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
487 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
488 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
489 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
490 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
491 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
492 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
493 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
494 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
495 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
496 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
498 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
499 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
500 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
501 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
502 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
503 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
504 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
505 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
507 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
508 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
509 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
510 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
511 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
512 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
515 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
517 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
518 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
519 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
520 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
521 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
522 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
523 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
526 * R10000 performance counter definitions.
528 * FIXME: The R10000 performance counter opens a nice way to implement CPU
529 * time accounting with a precission of one cycle. I don't have
530 * R10000 silicon but just a manual, so ...
534 * Events counted by counter #0
537 #define CE0_INSN_ISSUED 1
538 #define CE0_LPSC_ISSUED 2
539 #define CE0_S_ISSUED 3
540 #define CE0_SC_ISSUED 4
541 #define CE0_SC_FAILED 5
542 #define CE0_BRANCH_DECODED 6
543 #define CE0_QW_WB_SECONDARY 7
544 #define CE0_CORRECTED_ECC_ERRORS 8
545 #define CE0_ICACHE_MISSES 9
546 #define CE0_SCACHE_I_MISSES 10
547 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
548 #define CE0_EXT_INTERVENTIONS_REQ 12
549 #define CE0_EXT_INVALIDATE_REQ 13
550 #define CE0_VIRTUAL_COHERENCY_COND 14
551 #define CE0_INSN_GRADUATED 15
554 * Events counted by counter #1
557 #define CE1_INSN_GRADUATED 1
558 #define CE1_LPSC_GRADUATED 2
559 #define CE1_S_GRADUATED 3
560 #define CE1_SC_GRADUATED 4
561 #define CE1_FP_INSN_GRADUATED 5
562 #define CE1_QW_WB_PRIMARY 6
563 #define CE1_TLB_REFILL 7
564 #define CE1_BRANCH_MISSPREDICTED 8
565 #define CE1_DCACHE_MISS 9
566 #define CE1_SCACHE_D_MISSES 10
567 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
568 #define CE1_EXT_INTERVENTION_HITS 12
569 #define CE1_EXT_INVALIDATE_REQ 13
570 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
571 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
574 * These flags define in which privilege mode the counters count events
576 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
577 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
578 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
579 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
584 * Functions to access the R10000 performance counters. These are basically
585 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
586 * performance counter number encoded into bits 1 ... 5 of the instruction.
587 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
588 * disassembler these will look like an access to sel 0 or 1.
590 #define read_r10k_perf_cntr(counter) \
592 unsigned int __res; \
593 __asm__ __volatile__( \
601 #define write_r10k_perf_cntr(counter,val) \
603 __asm__ __volatile__( \
606 : "r" (val), "i" (counter)); \
609 #define read_r10k_perf_event(counter) \
611 unsigned int __res; \
612 __asm__ __volatile__( \
620 #define write_r10k_perf_cntl(counter,val) \
622 __asm__ __volatile__( \
625 : "r" (val), "i" (counter)); \
630 * Macros to access the system control coprocessor
633 #define __read_32bit_c0_register(source, sel) \
636 __asm__ __volatile__( \
637 "mfc0\t%0, " #source "\n\t" \
640 __asm__ __volatile__( \
642 "mfc0\t%0, " #source ", " #sel "\n\t" \
648 #define __read_64bit_c0_register(source, sel) \
649 ({ unsigned long long __res; \
650 if (sizeof(unsigned long) == 4) \
651 __res = __read_64bit_c0_split(source, sel); \
653 __asm__ __volatile__( \
655 "dmfc0\t%0, " #source "\n\t" \
659 __asm__ __volatile__( \
661 "dmfc0\t%0, " #source ", " #sel "\n\t" \
667 #define __write_32bit_c0_register(register, sel, value) \
670 __asm__ __volatile__( \
671 "mtc0\t%z0, " #register "\n\t" \
672 : : "Jr" ((unsigned int)value)); \
674 __asm__ __volatile__( \
676 "mtc0\t%z0, " #register ", " #sel "\n\t" \
678 : : "Jr" ((unsigned int)value)); \
681 #define __write_64bit_c0_register(register, sel, value) \
683 if (sizeof(unsigned long) == 4) \
684 __write_64bit_c0_split(register, sel, value); \
686 __asm__ __volatile__( \
688 "dmtc0\t%z0, " #register "\n\t" \
692 __asm__ __volatile__( \
694 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
699 #define __read_ulong_c0_register(reg, sel) \
700 ((sizeof(unsigned long) == 4) ? \
701 (unsigned long) __read_32bit_c0_register(reg, sel) : \
702 (unsigned long) __read_64bit_c0_register(reg, sel))
704 #define __write_ulong_c0_register(reg, sel, val) \
706 if (sizeof(unsigned long) == 4) \
707 __write_32bit_c0_register(reg, sel, val); \
709 __write_64bit_c0_register(reg, sel, val); \
713 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
715 #define __read_32bit_c0_ctrl_register(source) \
717 __asm__ __volatile__( \
718 "cfc0\t%0, " #source "\n\t" \
723 #define __write_32bit_c0_ctrl_register(register, value) \
725 __asm__ __volatile__( \
726 "ctc0\t%z0, " #register "\n\t" \
727 : : "Jr" ((unsigned int)value)); \
731 * These versions are only needed for systems with more than 38 bits of
732 * physical address space running the 32-bit kernel. That's none atm :-)
734 #define __read_64bit_c0_split(source, sel) \
736 unsigned long long val; \
737 unsigned long flags; \
739 local_irq_save(flags); \
741 __asm__ __volatile__( \
743 "dmfc0\t%M0, " #source "\n\t" \
744 "dsll\t%L0, %M0, 32\n\t" \
745 "dsrl\t%M0, %M0, 32\n\t" \
746 "dsrl\t%L0, %L0, 32\n\t" \
750 __asm__ __volatile__( \
752 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
753 "dsll\t%L0, %M0, 32\n\t" \
754 "dsrl\t%M0, %M0, 32\n\t" \
755 "dsrl\t%L0, %L0, 32\n\t" \
758 local_irq_restore(flags); \
763 #define __write_64bit_c0_split(source, sel, val) \
765 unsigned long flags; \
767 local_irq_save(flags); \
769 __asm__ __volatile__( \
771 "dsll\t%L0, %L0, 32\n\t" \
772 "dsrl\t%L0, %L0, 32\n\t" \
773 "dsll\t%M0, %M0, 32\n\t" \
774 "or\t%L0, %L0, %M0\n\t" \
775 "dmtc0\t%L0, " #source "\n\t" \
779 __asm__ __volatile__( \
781 "dsll\t%L0, %L0, 32\n\t" \
782 "dsrl\t%L0, %L0, 32\n\t" \
783 "dsll\t%M0, %M0, 32\n\t" \
784 "or\t%L0, %L0, %M0\n\t" \
785 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
788 local_irq_restore(flags); \
791 #define read_c0_index() __read_32bit_c0_register($0, 0)
792 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
794 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
795 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
797 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
798 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
800 #define read_c0_conf() __read_32bit_c0_register($3, 0)
801 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
803 #define read_c0_context() __read_ulong_c0_register($4, 0)
804 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
806 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
807 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
809 #define read_c0_wired() __read_32bit_c0_register($6, 0)
810 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
812 #define read_c0_info() __read_32bit_c0_register($7, 0)
814 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
815 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
817 #define read_c0_count() __read_32bit_c0_register($9, 0)
818 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
820 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
821 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
823 #define read_c0_compare() __read_32bit_c0_register($11, 0)
824 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
826 #define read_c0_status() __read_32bit_c0_register($12, 0)
827 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
829 #define read_c0_cause() __read_32bit_c0_register($13, 0)
830 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
832 #define read_c0_epc() __read_ulong_c0_register($14, 0)
833 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
835 #define read_c0_prid() __read_32bit_c0_register($15, 0)
837 #define read_c0_config() __read_32bit_c0_register($16, 0)
838 #define read_c0_config1() __read_32bit_c0_register($16, 1)
839 #define read_c0_config2() __read_32bit_c0_register($16, 2)
840 #define read_c0_config3() __read_32bit_c0_register($16, 3)
841 #define read_c0_config4() __read_32bit_c0_register($16, 4)
842 #define read_c0_config5() __read_32bit_c0_register($16, 5)
843 #define read_c0_config6() __read_32bit_c0_register($16, 6)
844 #define read_c0_config7() __read_32bit_c0_register($16, 7)
845 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
846 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
847 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
848 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
849 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
850 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
851 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
852 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
855 * The WatchLo register. There may be upto 8 of them.
857 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
858 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
859 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
860 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
861 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
862 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
863 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
864 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
865 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
866 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
867 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
868 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
869 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
870 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
871 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
872 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
875 * The WatchHi register. There may be upto 8 of them.
877 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
878 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
879 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
880 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
881 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
882 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
883 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
884 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
886 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
887 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
888 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
889 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
890 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
891 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
892 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
893 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
895 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
896 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
898 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
899 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
901 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
902 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
904 /* RM9000 PerfControl performance counter control register */
905 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
906 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
908 #define read_c0_diag() __read_32bit_c0_register($22, 0)
909 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
911 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
912 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
914 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
915 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
917 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
918 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
920 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
921 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
923 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
924 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
926 #define read_c0_debug() __read_32bit_c0_register($23, 0)
927 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
929 #define read_c0_depc() __read_ulong_c0_register($24, 0)
930 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
933 * MIPS32 / MIPS64 performance counters
935 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
936 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
937 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
938 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
939 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
940 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
941 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
942 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
943 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
944 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
945 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
946 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
947 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
948 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
949 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
950 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
952 /* RM9000 PerfCount performance counter register */
953 #define read_c0_perfcount() __read_64bit_c0_register($25, 0)
954 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
956 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
957 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
959 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
960 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
962 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
964 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
965 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
967 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
968 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
970 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
971 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
973 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
974 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
977 * Macros to access the floating point coprocessor control registers
979 #define read_32bit_cp1_register(source) \
981 __asm__ __volatile__( \
983 ".set\treorder\n\t" \
984 "cfc1\t%0,"STR(source)"\n\t" \
992 * It is responsibility of the caller to take care of any TLB hazards.
994 static inline void tlb_probe(void)
996 __asm__ __volatile__(
1002 static inline void tlb_read(void)
1004 __asm__ __volatile__(
1005 ".set noreorder\n\t"
1010 static inline void tlb_write_indexed(void)
1012 __asm__ __volatile__(
1013 ".set noreorder\n\t"
1018 static inline void tlb_write_random(void)
1020 __asm__ __volatile__(
1021 ".set noreorder\n\t"
1027 * Manipulate bits in a c0 register.
1029 #define __BUILD_SET_C0(name) \
1030 static inline unsigned int \
1031 set_c0_##name(unsigned int set) \
1035 res = read_c0_##name(); \
1037 write_c0_##name(res); \
1042 static inline unsigned int \
1043 clear_c0_##name(unsigned int clear) \
1047 res = read_c0_##name(); \
1049 write_c0_##name(res); \
1054 static inline unsigned int \
1055 change_c0_##name(unsigned int change, unsigned int new) \
1059 res = read_c0_##name(); \
1061 res |= (new & change); \
1062 write_c0_##name(res); \
1067 __BUILD_SET_C0(status)
1068 __BUILD_SET_C0(cause)
1069 __BUILD_SET_C0(config)
1070 __BUILD_SET_C0(intcontrol)
1072 #endif /* !__ASSEMBLY__ */
1074 #endif /* _ASM_MIPSREGS_H */