err.no Git - linux-2.6/blob - include/asm-mips/mipsmtregs.h

   1 /*
   2  * MT regs definitions, follows on from mipsregs.h
   3  * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
   4  * Elizabeth Clarke et. al.
   5  *
   6  */
   7 #ifndef _ASM_MIPSMTREGS_H
   8 #define _ASM_MIPSMTREGS_H
   9
  10 #include <asm/war.h>
  11
  12 #ifndef __ASSEMBLY__
  13
  14 /*
  15  * C macros
  16  */
  17
  18 #define read_c0_mvpcontrol()            __read_32bit_c0_register($0, 1)
  19 #define write_c0_mvpcontrol(val)        __write_32bit_c0_register($0, 1, val)
  20
  21 #define read_c0_mvpconf0()              __read_32bit_c0_register($0, 2)
  22 #define read_c0_mvpconf1()              __read_32bit_c0_register($0, 3)
  23
  24 #define read_c0_vpecontrol()            __read_32bit_c0_register($1, 1)
  25 #define write_c0_vpecontrol(val)        __write_32bit_c0_register($1, 1, val)
  26
  27 #define read_c0_vpeconf0()              __read_32bit_c0_register($1, 2)
  28 #define write_c0_vpeconf0(val)          __write_32bit_c0_register($1, 2, val)
  29
  30 #define read_c0_tcstatus()              __read_32bit_c0_register($2, 1)
  31 #define write_c0_tcstatus(val)          __write_32bit_c0_register($2, 1, val)
  32
  33 #define read_c0_tcbind()                __read_32bit_c0_register($2, 2)
  34
  35 #define read_c0_tccontext()             __read_32bit_c0_register($2, 5)
  36 #define write_c0_tccontext(val)         __write_32bit_c0_register($2, 5, val)
  37
  38 #else /* Assembly */
  39 /*
  40  * Macros for use in assembly language code
  41  */
  42
  43 #define CP0_MVPCONTROL          $0,1
  44 #define CP0_MVPCONF0            $0,2
  45 #define CP0_MVPCONF1            $0,3
  46 #define CP0_VPECONTROL          $1,1
  47 #define CP0_VPECONF0            $1,2
  48 #define CP0_VPECONF1            $1,3
  49 #define CP0_YQMASK              $1,4
  50 #define CP0_VPESCHEDULE $1,5
  51 #define CP0_VPESCHEFBK          $1,6
  52 #define CP0_TCSTATUS            $2,1
  53 #define CP0_TCBIND              $2,2
  54 #define CP0_TCRESTART           $2,3
  55 #define CP0_TCHALT              $2,4
  56 #define CP0_TCCONTEXT           $2,5
  57 #define CP0_TCSCHEDULE          $2,6
  58 #define CP0_TCSCHEFBK           $2,7
  59 #define CP0_SRSCONF0            $6,1
  60 #define CP0_SRSCONF1            $6,2
  61 #define CP0_SRSCONF2            $6,3
  62 #define CP0_SRSCONF3            $6,4
  63 #define CP0_SRSCONF4            $6,5
  64
  65 #endif
  66
  67 /* MVPControl fields */
  68 #define MVPCONTROL_EVP          (_ULCAST_(1))
  69
  70 #define MVPCONTROL_VPC_SHIFT    1
  71 #define MVPCONTROL_VPC          (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
  72
  73 #define MVPCONTROL_STLB_SHIFT   2
  74 #define MVPCONTROL_STLB         (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
  75
  76
  77 /* MVPConf0 fields */
  78 #define MVPCONF0_PTC_SHIFT      0
  79 #define MVPCONF0_PTC            ( _ULCAST_(0xff))
  80 #define MVPCONF0_PVPE_SHIFT     10
  81 #define MVPCONF0_PVPE           ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
  82 #define MVPCONF0_TCA_SHIFT      15
  83 #define MVPCONF0_TCA            ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
  84 #define MVPCONF0_PTLBE_SHIFT    16
  85 #define MVPCONF0_PTLBE          (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
  86 #define MVPCONF0_TLBS_SHIFT     29
  87 #define MVPCONF0_TLBS           (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
  88 #define MVPCONF0_M_SHIFT        31
  89 #define MVPCONF0_M              (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
  90
  91
  92 /* config3 fields */
  93 #define CONFIG3_MT_SHIFT        2
  94 #define CONFIG3_MT              (_ULCAST_(1) << CONFIG3_MT_SHIFT)
  95
  96
  97 /* VPEControl fields (per VPE) */
  98 #define VPECONTROL_TARGTC       (_ULCAST_(0xff))
  99
 100 #define VPECONTROL_TE_SHIFT     15
 101 #define VPECONTROL_TE           (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
 102 #define VPECONTROL_EXCPT_SHIFT  16
 103 #define VPECONTROL_EXCPT        (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
 104
 105 /* Thread Exception Codes for EXCPT field */
 106 #define THREX_TU                0
 107 #define THREX_TO                1
 108 #define THREX_IYQ               2
 109 #define THREX_GSX               3
 110 #define THREX_YSCH              4
 111 #define THREX_GSSCH             5
 112
 113 #define VPECONTROL_GSI_SHIFT    20
 114 #define VPECONTROL_GSI          (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
 115 #define VPECONTROL_YSI_SHIFT    21
 116 #define VPECONTROL_YSI          (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
 117
 118 /* VPEConf0 fields (per VPE) */
 119 #define VPECONF0_VPA_SHIFT      0
 120 #define VPECONF0_VPA            (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
 121 #define VPECONF0_MVP_SHIFT      1
 122 #define VPECONF0_MVP            (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
 123 #define VPECONF0_XTC_SHIFT      21
 124 #define VPECONF0_XTC            (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
 125
 126 /* TCStatus fields (per TC) */
 127 #define TCSTATUS_TASID          (_ULCAST_(0xff))
 128 #define TCSTATUS_IXMT_SHIFT     10
 129 #define TCSTATUS_IXMT           (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
 130 #define TCSTATUS_TKSU_SHIFT     11
 131 #define TCSTATUS_TKSU           (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
 132 #define TCSTATUS_A_SHIFT        13
 133 #define TCSTATUS_A              (_ULCAST_(1) << TCSTATUS_A_SHIFT)
 134 #define TCSTATUS_DA_SHIFT       15
 135 #define TCSTATUS_DA             (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
 136 #define TCSTATUS_DT_SHIFT       20
 137 #define TCSTATUS_DT             (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
 138 #define TCSTATUS_TDS_SHIFT      21
 139 #define TCSTATUS_TDS            (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
 140 #define TCSTATUS_TSST_SHIFT     22
 141 #define TCSTATUS_TSST           (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
 142 #define TCSTATUS_RNST_SHIFT     23
 143 #define TCSTATUS_RNST           (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
 144 /* Codes for RNST */
 145 #define TC_RUNNING              0
 146 #define TC_WAITING              1
 147 #define TC_YIELDING             2
 148 #define TC_GATED                3
 149
 150 #define TCSTATUS_TMX_SHIFT      27
 151 #define TCSTATUS_TMX            (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
 152 /* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
 153
 154 /* TCBind */
 155 #define TCBIND_CURVPE_SHIFT     0
 156 #define TCBIND_CURVPE           (_ULCAST_(0xf))
 157
 158 #define TCBIND_CURTC_SHIFT      21
 159
 160 #define TCBIND_CURTC            (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
 161
 162 /* TCHalt */
 163 #define TCHALT_H                (_ULCAST_(1))
 164
 165 #ifndef __ASSEMBLY__
 166
 167 extern void mips_mt_regdump(void);
 168
 169 static inline unsigned int dvpe(void)
 170 {
 171         int res = 0;
 172
 173         __asm__ __volatile__(
 174         "       .set    push                                            \n"
 175         "       .set    noreorder                                       \n"
 176         "       .set    noat                                            \n"
 177         "       .set    mips32r2                                        \n"
 178         "       move    $1, %0                                          \n"
 179         "       .word   0x41610001              # dvpe $1               \n"
 180         "       ehb                                                     \n"
 181         "       .set    pop                                             \n"
 182         : "=r" (res));
 183
 184         instruction_hazard();
 185
 186         return res;
 187 }
 188
 189 static inline void __raw_evpe(void)
 190 {
 191         __asm__ __volatile__(
 192         "       .set    push                                            \n"
 193         "       .set    noreorder                                       \n"
 194         "       .set    noat                                            \n"
 195         "       .set    mips32r2                                        \n"
 196         "       .word   0x41600021              # evpe                  \n"
 197         "       ehb                                                     \n"
 198         "       .set    pop                                             \n");
 199 }
 200
 201 /* Enable multiMT if previous suggested it should be.
 202    EMT_ENABLE to force */
 203
 204 #define EVPE_ENABLE MVPCONTROL_EVP
 205
 206 static inline void evpe(int previous)
 207 {
 208         if ((previous & MVPCONTROL_EVP))
 209                 __raw_evpe();
 210 }
 211
 212 static inline unsigned int dmt(void)
 213 {
 214         int res;
 215
 216         __asm__ __volatile__(
 217         "       .set    noreorder                                       \n"
 218         "       .set    mips32r2                                        \n"
 219         "       dmt     %0                                              \n"
 220         "       ehb                                                     \n"
 221         "       .set mips0                                              \n"
 222         "       .set reorder                                            \n"
 223         : "=r" (res));
 224
 225         instruction_hazard();
 226
 227         return res;
 228 }
 229
 230 static inline void __raw_emt(void)
 231 {
 232         __asm__ __volatile__(
 233         "       .set    noreorder                                       \n"
 234         "       .set    mips32r2                                        \n"
 235         "       emt                                                     \n"
 236         "       ehb                                                     \n"
 237         "       .set    mips0                                           \n"
 238         "       .set    reorder");
 239 }
 240
 241 /* enable multiVPE if previous suggested it should be.
 242    EVPE_ENABLE to force */
 243
 244 #define EMT_ENABLE VPECONTROL_TE
 245
 246 static inline void emt(int previous)
 247 {
 248         if ((previous & EMT_ENABLE))
 249                 __raw_emt();
 250 }
 251
 252 static inline void ehb(void)
 253 {
 254         __asm__ __volatile__("ehb");
 255 }
 256
 257 #define mftc0(rt,sel)                                                   \
 258 ({                                                                      \
 259          unsigned long  __res;                                          \
 260                                                                         \
 261         __asm__ __volatile__(                                           \
 262          "      .set noat\n\t"                                          \
 263          "      mftc0\t%0," #rt ", " #sel "\n\t"                        \
 264          "      .set at\n\t"                                            \
 265          : "=r" (__res));                                               \
 266                                                                         \
 267         __res;                                                          \
 268 })
 269
 270 #define mftgpr(rt)                                                      \
 271 ({                                                                      \
 272         unsigned long __res;                                            \
 273                                                                         \
 274         __asm__ __volatile__(                                           \
 275         "       .set    noat                                    \n"     \
 276         "       mftgpr  %0," #rt "                              \n"     \
 277         "       .set    at                                      \n"     \
 278         : "=r" (__res));                                                \
 279                                                                         \
 280         __res;                                                          \
 281 })
 282
 283 #define mftr(rt,u,sel)                                                  \
 284 ({                                                                      \
 285         unsigned long __res;                                            \
 286                                                                         \
 287         __asm__ __volatile__(                                           \
 288         ".set noat\n\t"                                                 \
 289         "mftr\t%0, " #rt ", " #u ", " #sel "\n\t"                       \
 290         ".set at\n\t"                                                   \
 291         : "=r" (__res));                                                \
 292                                                                         \
 293         __res;                                                          \
 294 })
 295
 296 #define mttgpr(rd,v)                                                    \
 297 ({                                                                      \
 298         __asm__ __volatile__(                                           \
 299         "mttgpr %0," #rd                                                \
 300         : : "r" (v));                                                   \
 301 })
 302
 303 #define mttc0(rd,sel,v)                                                 \
 304 ({                                                                      \
 305         __asm__ __volatile__(                                           \
 306         "mttc0\t %0," #rd ", " #sel                                     \
 307         : : "r" (v));                                                   \
 308 })
 309
 310
 311 #define mttr(rd,u,sel,v)                                                \
 312 ({                                                                      \
 313         __asm__ __volatile__(                                           \
 314         "mttr   %0," #rd ", " #u ", " #sel                              \
 315         : : "r" (v));                                                   \
 316 })
 317
 318
 319 #define settc(tc)                                                       \
 320 do {                                                                    \
 321         write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
 322         ehb();                                                          \
 323 } while (0)
 324
 325
 326 /* you *must* set the target tc (settc) before trying to use these */
 327 #define read_vpe_c0_vpecontrol()        mftc0($1, 1)
 328 #define write_vpe_c0_vpecontrol(val)    mttc0($1, 1, val)
 329 #define read_vpe_c0_vpeconf0()          mftc0($1, 2)
 330 #define write_vpe_c0_vpeconf0(val)      mttc0($1, 2, val)
 331 #define read_vpe_c0_status()            mftc0($12, 0)
 332 #define write_vpe_c0_status(val)        mttc0($12, 0, val)
 333 #define read_vpe_c0_cause()             mftc0($13, 0)
 334 #define write_vpe_c0_cause(val)         mttc0($13, 0, val)
 335 #define read_vpe_c0_config()            mftc0($16, 0)
 336 #define write_vpe_c0_config(val)        mttc0($16, 0, val)
 337 #define read_vpe_c0_config1()           mftc0($16, 1)
 338 #define write_vpe_c0_config1(val)       mttc0($16, 1, val)
 339 #define read_vpe_c0_config7()           mftc0($16, 7)
 340 #define write_vpe_c0_config7(val)       mttc0($16, 7, val)
 341 #define read_vpe_c0_ebase()             mftc0($15,1)
 342 #define write_vpe_c0_ebase(val)         mttc0($15, 1, val)
 343 #define write_vpe_c0_compare(val)       mttc0($11, 0, val)
 344
 345
 346 /* TC */
 347 #define read_tc_c0_tcstatus()           mftc0($2, 1)
 348 #define write_tc_c0_tcstatus(val)       mttc0($2,1,val)
 349 #define read_tc_c0_tcbind()             mftc0($2, 2)
 350 #define write_tc_c0_tcbind(val)         mttc0($2,2,val)
 351 #define read_tc_c0_tcrestart()          mftc0($2, 3)
 352 #define write_tc_c0_tcrestart(val)      mttc0($2,3,val)
 353 #define read_tc_c0_tchalt()             mftc0($2, 4)
 354 #define write_tc_c0_tchalt(val)         mttc0($2,4,val)
 355 #define read_tc_c0_tccontext()          mftc0($2, 5)
 356 #define write_tc_c0_tccontext(val)      mttc0($2,5,val)
 357
 358 /* GPR */
 359 #define read_tc_gpr_sp()                mftgpr($29)
 360 #define write_tc_gpr_sp(val)            mttgpr($29, val)
 361 #define read_tc_gpr_gp()                mftgpr($28)
 362 #define write_tc_gpr_gp(val)            mttgpr($28, val)
 363
 364
 365 #endif /* Not __ASSEMBLY__ */
 366
 367 #endif