3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2004 Embedded Edge, LLC
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 /* Specifics for the Au1xxx Programmable Serial Controllers, first
31 * seen in the AU1550 part.
33 #ifndef _AU1000_PSC_H_
34 #define _AU1000_PSC_H_
37 /* The PSC base addresses. */
38 #ifdef CONFIG_SOC_AU1550
39 #define PSC0_BASE_ADDR 0xb1a00000
40 #define PSC1_BASE_ADDR 0xb1b00000
41 #define PSC2_BASE_ADDR 0xb0a00000
42 #define PSC3_BASE_ADDR 0xb0d00000
45 /* The PSC select and control registers are common to
48 #define PSC_SEL_OFFSET 0x00000000
49 #define PSC_CTRL_OFFSET 0x00000004
51 #define PSC_SEL_CLK_MASK (3 << 4)
52 #define PSC_SEL_CLK_INTCLK (0 << 4)
53 #define PSC_SEL_CLK_EXTCLK (1 << 4)
54 #define PSC_SEL_CLK_SERCLK (2 << 4)
56 #define PSC_SEL_PS_MASK 0x00000007
57 #define PSC_SEL_PS_DISABLED (0)
58 #define PSC_SEL_PS_SPIMODE (2)
59 #define PSC_SEL_PS_I2SMODE (3)
60 #define PSC_SEL_PS_AC97MODE (4)
61 #define PSC_SEL_PS_SMBUSMODE (5)
63 #define PSC_CTRL_DISABLE (0)
64 #define PSC_CTRL_SUSPEND (2)
65 #define PSC_CTRL_ENABLE (3)
69 #define PSC_AC97CFG_OFFSET 0x00000008
70 #define PSC_AC97MSK_OFFSET 0x0000000c
71 #define PSC_AC97PCR_OFFSET 0x00000010
72 #define PSC_AC97STAT_OFFSET 0x00000014
73 #define PSC_AC97EVNT_OFFSET 0x00000018
74 #define PSC_AC97TXRX_OFFSET 0x0000001c
75 #define PSC_AC97CDC_OFFSET 0x00000020
76 #define PSC_AC97RST_OFFSET 0x00000024
77 #define PSC_AC97GPO_OFFSET 0x00000028
78 #define PSC_AC97GPI_OFFSET 0x0000002c
80 #define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
81 #define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
82 #define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
83 #define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
84 #define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
85 #define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
86 #define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
87 #define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
88 #define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
89 #define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
90 #define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
91 #define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
93 /* AC97 Config Register.
95 #define PSC_AC97CFG_RT_MASK (3 << 30)
96 #define PSC_AC97CFG_RT_FIFO1 (0 << 30)
97 #define PSC_AC97CFG_RT_FIFO2 (1 << 30)
98 #define PSC_AC97CFG_RT_FIFO4 (2 << 30)
99 #define PSC_AC97CFG_RT_FIFO8 (3 << 30)
101 #define PSC_AC97CFG_TT_MASK (3 << 28)
102 #define PSC_AC97CFG_TT_FIFO1 (0 << 28)
103 #define PSC_AC97CFG_TT_FIFO2 (1 << 28)
104 #define PSC_AC97CFG_TT_FIFO4 (2 << 28)
105 #define PSC_AC97CFG_TT_FIFO8 (3 << 28)
107 #define PSC_AC97CFG_DD_DISABLE (1 << 27)
108 #define PSC_AC97CFG_DE_ENABLE (1 << 26)
109 #define PSC_AC97CFG_SE_ENABLE (1 << 25)
111 #define PSC_AC97CFG_LEN_MASK (0xf << 21)
112 #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
113 #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
114 #define PSC_AC97CFG_GE_ENABLE (1)
116 /* Enable slots 3-12.
118 #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
119 #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
121 /* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
122 * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
123 * arithmetic in the macro.
125 #define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21)
126 #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
128 /* AC97 Mask Register.
130 #define PSC_AC97MSK_GR (1 << 25)
131 #define PSC_AC97MSK_CD (1 << 24)
132 #define PSC_AC97MSK_RR (1 << 13)
133 #define PSC_AC97MSK_RO (1 << 12)
134 #define PSC_AC97MSK_RU (1 << 11)
135 #define PSC_AC97MSK_TR (1 << 10)
136 #define PSC_AC97MSK_TO (1 << 9)
137 #define PSC_AC97MSK_TU (1 << 8)
138 #define PSC_AC97MSK_RD (1 << 5)
139 #define PSC_AC97MSK_TD (1 << 4)
140 #define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
141 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
142 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
143 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
144 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
146 /* AC97 Protocol Control Register.
148 #define PSC_AC97PCR_RC (1 << 6)
149 #define PSC_AC97PCR_RP (1 << 5)
150 #define PSC_AC97PCR_RS (1 << 4)
151 #define PSC_AC97PCR_TC (1 << 2)
152 #define PSC_AC97PCR_TP (1 << 1)
153 #define PSC_AC97PCR_TS (1 << 0)
155 /* AC97 Status register (read only).
157 #define PSC_AC97STAT_CB (1 << 26)
158 #define PSC_AC97STAT_CP (1 << 25)
159 #define PSC_AC97STAT_CR (1 << 24)
160 #define PSC_AC97STAT_RF (1 << 13)
161 #define PSC_AC97STAT_RE (1 << 12)
162 #define PSC_AC97STAT_RR (1 << 11)
163 #define PSC_AC97STAT_TF (1 << 10)
164 #define PSC_AC97STAT_TE (1 << 9)
165 #define PSC_AC97STAT_TR (1 << 8)
166 #define PSC_AC97STAT_RB (1 << 5)
167 #define PSC_AC97STAT_TB (1 << 4)
168 #define PSC_AC97STAT_DI (1 << 2)
169 #define PSC_AC97STAT_DR (1 << 1)
170 #define PSC_AC97STAT_SR (1 << 0)
172 /* AC97 Event Register.
174 #define PSC_AC97EVNT_GR (1 << 25)
175 #define PSC_AC97EVNT_CD (1 << 24)
176 #define PSC_AC97EVNT_RR (1 << 13)
177 #define PSC_AC97EVNT_RO (1 << 12)
178 #define PSC_AC97EVNT_RU (1 << 11)
179 #define PSC_AC97EVNT_TR (1 << 10)
180 #define PSC_AC97EVNT_TO (1 << 9)
181 #define PSC_AC97EVNT_TU (1 << 8)
182 #define PSC_AC97EVNT_RD (1 << 5)
183 #define PSC_AC97EVNT_TD (1 << 4)
185 /* CODEC Command Register.
187 #define PSC_AC97CDC_RD (1 << 25)
188 #define PSC_AC97CDC_ID_MASK (3 << 23)
189 #define PSC_AC97CDC_INDX_MASK (0x7f << 16)
190 #define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23)
191 #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
193 /* AC97 Reset Control Register.
195 #define PSC_AC97RST_RST (1 << 1)
196 #define PSC_AC97RST_SNC (1 << 0)
201 typedef struct psc_i2s {
213 /* I2S Config Register.
215 #define PSC_I2SCFG_RT_MASK (3 << 30)
216 #define PSC_I2SCFG_RT_FIFO1 (0 << 30)
217 #define PSC_I2SCFG_RT_FIFO2 (1 << 30)
218 #define PSC_I2SCFG_RT_FIFO4 (2 << 30)
219 #define PSC_I2SCFG_RT_FIFO8 (3 << 30)
221 #define PSC_I2SCFG_TT_MASK (3 << 28)
222 #define PSC_I2SCFG_TT_FIFO1 (0 << 28)
223 #define PSC_I2SCFG_TT_FIFO2 (1 << 28)
224 #define PSC_I2SCFG_TT_FIFO4 (2 << 28)
225 #define PSC_I2SCFG_TT_FIFO8 (3 << 28)
227 #define PSC_I2SCFG_DD_DISABLE (1 << 27)
228 #define PSC_I2SCFG_DE_ENABLE (1 << 26)
229 #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16)
230 #define PSC_I2SCFG_WI (1 << 15)
232 #define PSC_I2SCFG_DIV_MASK (3 << 13)
233 #define PSC_I2SCFG_DIV2 (0 << 13)
234 #define PSC_I2SCFG_DIV4 (1 << 13)
235 #define PSC_I2SCFG_DIV8 (2 << 13)
236 #define PSC_I2SCFG_DIV16 (3 << 13)
238 #define PSC_I2SCFG_BI (1 << 12)
239 #define PSC_I2SCFG_BUF (1 << 11)
240 #define PSC_I2SCFG_MLJ (1 << 10)
241 #define PSC_I2SCFG_XM (1 << 9)
243 /* The word length equation is simply LEN+1.
245 #define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
246 #define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
248 #define PSC_I2SCFG_LB (1 << 2)
249 #define PSC_I2SCFG_MLF (1 << 1)
250 #define PSC_I2SCFG_MS (1 << 0)
252 /* I2S Mask Register.
254 #define PSC_I2SMSK_RR (1 << 13)
255 #define PSC_I2SMSK_RO (1 << 12)
256 #define PSC_I2SMSK_RU (1 << 11)
257 #define PSC_I2SMSK_TR (1 << 10)
258 #define PSC_I2SMSK_TO (1 << 9)
259 #define PSC_I2SMSK_TU (1 << 8)
260 #define PSC_I2SMSK_RD (1 << 5)
261 #define PSC_I2SMSK_TD (1 << 4)
262 #define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
263 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
264 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
265 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
267 /* I2S Protocol Control Register.
269 #define PSC_I2SPCR_RC (1 << 6)
270 #define PSC_I2SPCR_RP (1 << 5)
271 #define PSC_I2SPCR_RS (1 << 4)
272 #define PSC_I2SPCR_TC (1 << 2)
273 #define PSC_I2SPCR_TP (1 << 1)
274 #define PSC_I2SPCR_TS (1 << 0)
276 /* I2S Status register (read only).
278 #define PSC_I2SSTAT_RF (1 << 13)
279 #define PSC_I2SSTAT_RE (1 << 12)
280 #define PSC_I2SSTAT_RR (1 << 11)
281 #define PSC_I2SSTAT_TF (1 << 10)
282 #define PSC_I2SSTAT_TE (1 << 9)
283 #define PSC_I2SSTAT_TR (1 << 8)
284 #define PSC_I2SSTAT_RB (1 << 5)
285 #define PSC_I2SSTAT_TB (1 << 4)
286 #define PSC_I2SSTAT_DI (1 << 2)
287 #define PSC_I2SSTAT_DR (1 << 1)
288 #define PSC_I2SSTAT_SR (1 << 0)
290 /* I2S Event Register.
292 #define PSC_I2SEVNT_RR (1 << 13)
293 #define PSC_I2SEVNT_RO (1 << 12)
294 #define PSC_I2SEVNT_RU (1 << 11)
295 #define PSC_I2SEVNT_TR (1 << 10)
296 #define PSC_I2SEVNT_TO (1 << 9)
297 #define PSC_I2SEVNT_TU (1 << 8)
298 #define PSC_I2SEVNT_RD (1 << 5)
299 #define PSC_I2SEVNT_TD (1 << 4)
303 typedef struct psc_spi {
314 /* SPI Config Register.
316 #define PSC_SPICFG_RT_MASK (3 << 30)
317 #define PSC_SPICFG_RT_FIFO1 (0 << 30)
318 #define PSC_SPICFG_RT_FIFO2 (1 << 30)
319 #define PSC_SPICFG_RT_FIFO4 (2 << 30)
320 #define PSC_SPICFG_RT_FIFO8 (3 << 30)
322 #define PSC_SPICFG_TT_MASK (3 << 28)
323 #define PSC_SPICFG_TT_FIFO1 (0 << 28)
324 #define PSC_SPICFG_TT_FIFO2 (1 << 28)
325 #define PSC_SPICFG_TT_FIFO4 (2 << 28)
326 #define PSC_SPICFG_TT_FIFO8 (3 << 28)
328 #define PSC_SPICFG_DD_DISABLE (1 << 27)
329 #define PSC_SPICFG_DE_ENABLE (1 << 26)
330 #define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15))
331 #define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15)
333 #define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13)
334 #define PSC_SPICFG_DIV2 0
335 #define PSC_SPICFG_DIV4 1
336 #define PSC_SPICFG_DIV8 2
337 #define PSC_SPICFG_DIV16 3
339 #define PSC_SPICFG_BI (1 << 12)
340 #define PSC_SPICFG_PSE (1 << 11)
341 #define PSC_SPICFG_CGE (1 << 10)
342 #define PSC_SPICFG_CDE (1 << 9)
344 #define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4))
345 #define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4)
347 #define PSC_SPICFG_LB (1 << 3)
348 #define PSC_SPICFG_MLF (1 << 1)
349 #define PSC_SPICFG_MO (1 << 0)
351 /* SPI Mask Register.
353 #define PSC_SPIMSK_MM (1 << 16)
354 #define PSC_SPIMSK_RR (1 << 13)
355 #define PSC_SPIMSK_RO (1 << 12)
356 #define PSC_SPIMSK_RU (1 << 11)
357 #define PSC_SPIMSK_TR (1 << 10)
358 #define PSC_SPIMSK_TO (1 << 9)
359 #define PSC_SPIMSK_TU (1 << 8)
360 #define PSC_SPIMSK_SD (1 << 5)
361 #define PSC_SPIMSK_MD (1 << 4)
362 #define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
363 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
364 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
367 /* SPI Protocol Control Register.
369 #define PSC_SPIPCR_RC (1 << 6)
370 #define PSC_SPIPCR_SP (1 << 5)
371 #define PSC_SPIPCR_SS (1 << 4)
372 #define PSC_SPIPCR_TC (1 << 2)
373 #define PSC_SPIPCR_MS (1 << 0)
375 /* SPI Status register (read only).
377 #define PSC_SPISTAT_RF (1 << 13)
378 #define PSC_SPISTAT_RE (1 << 12)
379 #define PSC_SPISTAT_RR (1 << 11)
380 #define PSC_SPISTAT_TF (1 << 10)
381 #define PSC_SPISTAT_TE (1 << 9)
382 #define PSC_SPISTAT_TR (1 << 8)
383 #define PSC_SPISTAT_SB (1 << 5)
384 #define PSC_SPISTAT_MB (1 << 4)
385 #define PSC_SPISTAT_DI (1 << 2)
386 #define PSC_SPISTAT_DR (1 << 1)
387 #define PSC_SPISTAT_SR (1 << 0)
389 /* SPI Event Register.
391 #define PSC_SPIEVNT_MM (1 << 16)
392 #define PSC_SPIEVNT_RR (1 << 13)
393 #define PSC_SPIEVNT_RO (1 << 12)
394 #define PSC_SPIEVNT_RU (1 << 11)
395 #define PSC_SPIEVNT_TR (1 << 10)
396 #define PSC_SPIEVNT_TO (1 << 9)
397 #define PSC_SPIEVNT_TU (1 << 8)
398 #define PSC_SPIEVNT_SD (1 << 5)
399 #define PSC_SPIEVNT_MD (1 << 4)
401 /* Transmit register control.
403 #define PSC_SPITXRX_LC (1 << 29)
404 #define PSC_SPITXRX_SR (1 << 28)
406 /* PSC in SMBus (I2C) Mode.
408 typedef struct psc_smb {
420 /* SMBus Config Register.
422 #define PSC_SMBCFG_RT_MASK (3 << 30)
423 #define PSC_SMBCFG_RT_FIFO1 (0 << 30)
424 #define PSC_SMBCFG_RT_FIFO2 (1 << 30)
425 #define PSC_SMBCFG_RT_FIFO4 (2 << 30)
426 #define PSC_SMBCFG_RT_FIFO8 (3 << 30)
428 #define PSC_SMBCFG_TT_MASK (3 << 28)
429 #define PSC_SMBCFG_TT_FIFO1 (0 << 28)
430 #define PSC_SMBCFG_TT_FIFO2 (1 << 28)
431 #define PSC_SMBCFG_TT_FIFO4 (2 << 28)
432 #define PSC_SMBCFG_TT_FIFO8 (3 << 28)
434 #define PSC_SMBCFG_DD_DISABLE (1 << 27)
435 #define PSC_SMBCFG_DE_ENABLE (1 << 26)
437 #define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13)
438 #define PSC_SMBCFG_DIV2 0
439 #define PSC_SMBCFG_DIV4 1
440 #define PSC_SMBCFG_DIV8 2
441 #define PSC_SMBCFG_DIV16 3
443 #define PSC_SMBCFG_GCE (1 << 9)
444 #define PSC_SMBCFG_SFM (1 << 8)
446 #define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
448 /* SMBus Mask Register.
450 #define PSC_SMBMSK_DN (1 << 30)
451 #define PSC_SMBMSK_AN (1 << 29)
452 #define PSC_SMBMSK_AL (1 << 28)
453 #define PSC_SMBMSK_RR (1 << 13)
454 #define PSC_SMBMSK_RO (1 << 12)
455 #define PSC_SMBMSK_RU (1 << 11)
456 #define PSC_SMBMSK_TR (1 << 10)
457 #define PSC_SMBMSK_TO (1 << 9)
458 #define PSC_SMBMSK_TU (1 << 8)
459 #define PSC_SMBMSK_SD (1 << 5)
460 #define PSC_SMBMSK_MD (1 << 4)
461 #define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
462 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
463 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
464 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
467 /* SMBus Protocol Control Register.
469 #define PSC_SMBPCR_DC (1 << 2)
470 #define PSC_SMBPCR_MS (1 << 0)
472 /* SMBus Status register (read only).
474 #define PSC_SMBSTAT_BB (1 << 28)
475 #define PSC_SMBSTAT_RF (1 << 13)
476 #define PSC_SMBSTAT_RE (1 << 12)
477 #define PSC_SMBSTAT_RR (1 << 11)
478 #define PSC_SMBSTAT_TF (1 << 10)
479 #define PSC_SMBSTAT_TE (1 << 9)
480 #define PSC_SMBSTAT_TR (1 << 8)
481 #define PSC_SMBSTAT_SB (1 << 5)
482 #define PSC_SMBSTAT_MB (1 << 4)
483 #define PSC_SMBSTAT_DI (1 << 2)
484 #define PSC_SMBSTAT_DR (1 << 1)
485 #define PSC_SMBSTAT_SR (1 << 0)
487 /* SMBus Event Register.
489 #define PSC_SMBEVNT_DN (1 << 30)
490 #define PSC_SMBEVNT_AN (1 << 29)
491 #define PSC_SMBEVNT_AL (1 << 28)
492 #define PSC_SMBEVNT_RR (1 << 13)
493 #define PSC_SMBEVNT_RO (1 << 12)
494 #define PSC_SMBEVNT_RU (1 << 11)
495 #define PSC_SMBEVNT_TR (1 << 10)
496 #define PSC_SMBEVNT_TO (1 << 9)
497 #define PSC_SMBEVNT_TU (1 << 8)
498 #define PSC_SMBEVNT_SD (1 << 5)
499 #define PSC_SMBEVNT_MD (1 << 4)
500 #define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
501 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
502 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
503 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
506 /* Transmit register control.
508 #define PSC_SMBTXRX_RSR (1 << 30)
509 #define PSC_SMBTXRX_STP (1 << 29)
510 #define PSC_SMBTXRX_DATAMASK (0xff)
512 /* SMBus protocol timers register.
514 #define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30)
515 #define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
516 #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
517 #define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
518 #define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10)
519 #define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
520 #define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
523 #endif /* _AU1000_PSC_H_ */