2 * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
33 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
34 #define DMA_WAIT_TIMEOUT 100
35 #define NUM_DESCRIPTORS PRD_ENTRIES
36 #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
37 #define NUM_DESCRIPTORS 2
40 #ifndef AU1XXX_ATA_RQSIZE
41 #define AU1XXX_ATA_RQSIZE 128
44 /* Disable Burstable-Support for DBDMA */
45 #ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
46 #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
51 * This will enable the device to be powered up when write() or read()
52 * is called. If this is not defined, the driver will return -EBUSY.
54 #define WAKE_ON_ACCESS 1
58 spinlock_t lock; /* Used to block on state transitions */
59 au1xxx_power_dev_t *dev; /* Power Managers device structure */
60 unsigned stopped; /* USed to signaling device is stopped */
67 u32 tx_dev_id, rx_dev_id, target_dev_id;
69 void *tx_desc_head, *rx_desc_head;
71 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
73 struct dbdma_cmd *dma_table_cpu;
74 dma_addr_t dma_table_dma;
83 /*******************************************************************************
84 * PIO Mode timing calculation : *
86 * Static Bus Spec ATA Spec *
96 *******************************************************************************/
98 #define TCSOE_MASK (0x07<<29)
99 #define TOECS_MASK (0x07<<26)
100 #define TWCS_MASK (0x07<<28)
101 #define TCSH_MASK (0x0F<<24)
102 #define TCSOFF_MASK (0x07<<20)
103 #define TWP_MASK (0x3F<<14)
104 #define TCSW_MASK (0x0F<<10)
105 #define TPM_MASK (0x0F<<6)
106 #define TA_MASK (0x3F<<0)
107 #define TS_MASK (1<<8)
109 /* Timing parameters PIO mode 0 */
110 #define SBC_IDE_PIO0_TCSOE (0x04<<29)
111 #define SBC_IDE_PIO0_TOECS (0x01<<26)
112 #define SBC_IDE_PIO0_TWCS (0x02<<28)
113 #define SBC_IDE_PIO0_TCSH (0x08<<24)
114 #define SBC_IDE_PIO0_TCSOFF (0x07<<20)
115 #define SBC_IDE_PIO0_TWP (0x10<<14)
116 #define SBC_IDE_PIO0_TCSW (0x04<<10)
117 #define SBC_IDE_PIO0_TPM (0x0<<6)
118 #define SBC_IDE_PIO0_TA (0x15<<0)
119 /* Timing parameters PIO mode 1 */
120 #define SBC_IDE_PIO1_TCSOE (0x03<<29)
121 #define SBC_IDE_PIO1_TOECS (0x01<<26)
122 #define SBC_IDE_PIO1_TWCS (0x01<<28)
123 #define SBC_IDE_PIO1_TCSH (0x06<<24)
124 #define SBC_IDE_PIO1_TCSOFF (0x06<<20)
125 #define SBC_IDE_PIO1_TWP (0x08<<14)
126 #define SBC_IDE_PIO1_TCSW (0x03<<10)
127 #define SBC_IDE_PIO1_TPM (0x00<<6)
128 #define SBC_IDE_PIO1_TA (0x0B<<0)
129 /* Timing parameters PIO mode 2 */
130 #define SBC_IDE_PIO2_TCSOE (0x05<<29)
131 #define SBC_IDE_PIO2_TOECS (0x01<<26)
132 #define SBC_IDE_PIO2_TWCS (0x01<<28)
133 #define SBC_IDE_PIO2_TCSH (0x07<<24)
134 #define SBC_IDE_PIO2_TCSOFF (0x07<<20)
135 #define SBC_IDE_PIO2_TWP (0x1F<<14)
136 #define SBC_IDE_PIO2_TCSW (0x05<<10)
137 #define SBC_IDE_PIO2_TPM (0x00<<6)
138 #define SBC_IDE_PIO2_TA (0x22<<0)
139 /* Timing parameters PIO mode 3 */
140 #define SBC_IDE_PIO3_TCSOE (0x05<<29)
141 #define SBC_IDE_PIO3_TOECS (0x01<<26)
142 #define SBC_IDE_PIO3_TWCS (0x01<<28)
143 #define SBC_IDE_PIO3_TCSH (0x0D<<24)
144 #define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
145 #define SBC_IDE_PIO3_TWP (0x15<<14)
146 #define SBC_IDE_PIO3_TCSW (0x05<<10)
147 #define SBC_IDE_PIO3_TPM (0x00<<6)
148 #define SBC_IDE_PIO3_TA (0x1A<<0)
149 /* Timing parameters PIO mode 4 */
150 #define SBC_IDE_PIO4_TCSOE (0x04<<29)
151 #define SBC_IDE_PIO4_TOECS (0x01<<26)
152 #define SBC_IDE_PIO4_TWCS (0x01<<28)
153 #define SBC_IDE_PIO4_TCSH (0x04<<24)
154 #define SBC_IDE_PIO4_TCSOFF (0x04<<20)
155 #define SBC_IDE_PIO4_TWP (0x0D<<14)
156 #define SBC_IDE_PIO4_TCSW (0x03<<10)
157 #define SBC_IDE_PIO4_TPM (0x00<<6)
158 #define SBC_IDE_PIO4_TA (0x12<<0)
159 /* Timing parameters MDMA mode 0 */
160 #define SBC_IDE_MDMA0_TCSOE (0x03<<29)
161 #define SBC_IDE_MDMA0_TOECS (0x01<<26)
162 #define SBC_IDE_MDMA0_TWCS (0x01<<28)
163 #define SBC_IDE_MDMA0_TCSH (0x07<<24)
164 #define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
165 #define SBC_IDE_MDMA0_TWP (0x0C<<14)
166 #define SBC_IDE_MDMA0_TCSW (0x03<<10)
167 #define SBC_IDE_MDMA0_TPM (0x00<<6)
168 #define SBC_IDE_MDMA0_TA (0x0F<<0)
169 /* Timing parameters MDMA mode 1 */
170 #define SBC_IDE_MDMA1_TCSOE (0x05<<29)
171 #define SBC_IDE_MDMA1_TOECS (0x01<<26)
172 #define SBC_IDE_MDMA1_TWCS (0x01<<28)
173 #define SBC_IDE_MDMA1_TCSH (0x05<<24)
174 #define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
175 #define SBC_IDE_MDMA1_TWP (0x0F<<14)
176 #define SBC_IDE_MDMA1_TCSW (0x05<<10)
177 #define SBC_IDE_MDMA1_TPM (0x00<<6)
178 #define SBC_IDE_MDMA1_TA (0x15<<0)
179 /* Timing parameters MDMA mode 2 */
180 #define SBC_IDE_MDMA2_TCSOE (0x04<<29)
181 #define SBC_IDE_MDMA2_TOECS (0x01<<26)
182 #define SBC_IDE_MDMA2_TWCS (0x01<<28)
183 #define SBC_IDE_MDMA2_TCSH (0x04<<24)
184 #define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
185 #define SBC_IDE_MDMA2_TWP (0x0D<<14)
186 #define SBC_IDE_MDMA2_TCSW (0x04<<10)
187 #define SBC_IDE_MDMA2_TPM (0x00<<6)
188 #define SBC_IDE_MDMA2_TA (0x12<<0)
190 #define SBC_IDE_TIMING(mode) \
191 SBC_IDE_##mode##_TWCS | \
192 SBC_IDE_##mode##_TCSH | \
193 SBC_IDE_##mode##_TCSOFF | \
194 SBC_IDE_##mode##_TWP | \
195 SBC_IDE_##mode##_TCSW | \
196 SBC_IDE_##mode##_TPM | \