2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
15 #include <linux/config.h>
16 #include <linux/compiler.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
20 #include <asm/addrspace.h>
21 #include <asm/byteorder.h>
23 #include <asm/cpu-features.h>
25 #include <asm/pgtable-bits.h>
26 #include <asm/processor.h>
27 #include <asm/string.h>
30 #include <mangle-port.h>
33 * Slowdown I/O port space accesses for antique hardware.
35 #undef CONF_SLOWDOWN_IO
38 * Raw operations are never swapped in software. OTOH values that raw
39 * operations are working on may or may not have been swapped by the bus
40 * hardware. An example use would be for flash memory that's used for
43 # define __raw_ioswabb(x) (x)
44 # define __raw_ioswabw(x) (x)
45 # define __raw_ioswabl(x) (x)
46 # define __raw_ioswabq(x) (x)
47 # define ____raw_ioswabq(x) (x)
50 * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
51 * less sane hardware forces software to fiddle with this...
53 * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
54 * you can't have the numerical value of data and byte addresses within
55 * multibyte quantities both preserved at the same time. Hence two
56 * variations of functions: non-prefixed ones that preserve the value
57 * and prefixed ones that preserve byte addresses. The latters are
58 * typically used for moving raw data between a peripheral and memory (cf.
59 * string I/O functions), hence the "__mem_" prefix.
61 #if defined(CONFIG_SWAP_IO_SPACE)
63 # define ioswabb(x) (x)
64 # define __mem_ioswabb(x) (x)
65 # ifdef CONFIG_SGI_IP22
67 * IP22 seems braindead enough to swap 16bits values in hardware, but
68 * not 32bits. Go figure... Can't tell without documentation.
70 # define ioswabw(x) (x)
71 # define __mem_ioswabw(x) le16_to_cpu(x)
73 # define ioswabw(x) le16_to_cpu(x)
74 # define __mem_ioswabw(x) (x)
76 # define ioswabl(x) le32_to_cpu(x)
77 # define __mem_ioswabl(x) (x)
78 # define ioswabq(x) le64_to_cpu(x)
79 # define __mem_ioswabq(x) (x)
83 # define ioswabb(x) (x)
84 # define __mem_ioswabb(x) (x)
85 # define ioswabw(x) (x)
86 # define __mem_ioswabw(x) cpu_to_le16(x)
87 # define ioswabl(x) (x)
88 # define __mem_ioswabl(x) cpu_to_le32(x)
89 # define ioswabq(x) (x)
90 # define __mem_ioswabq(x) cpu_to_le32(x)
94 #define IO_SPACE_LIMIT 0xffff
97 * On MIPS I/O ports are memory mapped, so we access them using normal
98 * load/store instructions. mips_io_port_base is the virtual address to
99 * which all ports are being mapped. For sake of efficiency some code
100 * assumes that this is an address that can be loaded with a single lui
101 * instruction, so the lower 16 bits must be zero. Should be true on
102 * on any sane architecture; generic code does not use this assumption.
104 extern const unsigned long mips_io_port_base;
106 #define set_io_port_base(base) \
107 do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
110 * Thanks to James van Artsdalen for a better timing-fix than
111 * the two short jumps: using outb's to a nonexistent port seems
112 * to guarantee better timings even on fast machines.
114 * On the other hand, I'd like to be sure of a non-existent port:
115 * I feel a bit unsafe about using 0x80 (should be safe, though)
121 #define __SLOW_DOWN_IO \
122 __asm__ __volatile__( \
124 : : "r" (mips_io_port_base));
126 #ifdef CONF_SLOWDOWN_IO
127 #ifdef REALLY_SLOW_IO
128 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
130 #define SLOW_DOWN_IO __SLOW_DOWN_IO
137 * virt_to_phys - map virtual addresses to physical
138 * @address: address to remap
140 * The returned physical address is the physical (CPU) mapping for
141 * the memory address given. It is only valid to use this function on
142 * addresses directly mapped or allocated via kmalloc.
144 * This function does not give bus mappings for DMA transfers. In
145 * almost all conceivable cases a device driver should not be using
148 static inline unsigned long virt_to_phys(volatile void * address)
150 return (unsigned long)address - PAGE_OFFSET;
154 * phys_to_virt - map physical address to virtual
155 * @address: address to remap
157 * The returned virtual address is a current CPU mapping for
158 * the memory address given. It is only valid to use this function on
159 * addresses that have a kernel mapping
161 * This function does not handle bus mappings for DMA transfers. In
162 * almost all conceivable cases a device driver should not be using
165 static inline void * phys_to_virt(unsigned long address)
167 return (void *)(address + PAGE_OFFSET);
171 * ISA I/O bus memory addresses are 1:1 with the physical address.
173 static inline unsigned long isa_virt_to_bus(volatile void * address)
175 return (unsigned long)address - PAGE_OFFSET;
178 static inline void * isa_bus_to_virt(unsigned long address)
180 return (void *)(address + PAGE_OFFSET);
183 #define isa_page_to_bus page_to_phys
186 * However PCI ones are not necessarily 1:1 and therefore these interfaces
187 * are forbidden in portable PCI drivers.
189 * Allow them for x86 for legacy drivers, though.
191 #define virt_to_bus virt_to_phys
192 #define bus_to_virt phys_to_virt
195 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
196 * for the processor. This implies the assumption that there is only
197 * one of these busses.
199 extern unsigned long isa_slot_offset;
202 * Change "struct page" to physical address.
204 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
206 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
207 extern void __iounmap(volatile void __iomem *addr);
209 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
212 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
214 if (cpu_has_64bit_addresses) {
215 u64 base = UNCAC_BASE;
218 * R10000 supports a 2 bit uncached attribute therefore
219 * UNCAC_BASE may not equal IO_BASE.
221 if (flags == _CACHE_UNCACHED)
222 base = (u64) IO_BASE;
223 return (void __iomem *) (unsigned long) (base + offset);
224 } else if (__builtin_constant_p(offset) &&
225 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
226 phys_t phys_addr, last_addr;
228 phys_addr = fixup_bigphys_addr(offset, size);
230 /* Don't allow wraparound or zero size. */
231 last_addr = phys_addr + size - 1;
232 if (!size || last_addr < phys_addr)
236 * Map uncached objects in the low 512MB of address
239 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
240 flags == _CACHE_UNCACHED)
241 return (void __iomem *)CKSEG1ADDR(phys_addr);
244 return __ioremap(offset, size, flags);
250 * ioremap - map bus memory into CPU space
251 * @offset: bus address of the memory
252 * @size: size of the resource to map
254 * ioremap performs a platform specific sequence of operations to
255 * make bus memory CPU accessible via the readb/readw/readl/writeb/
256 * writew/writel functions and the other mmio helpers. The returned
257 * address is not guaranteed to be usable directly as a virtual
260 #define ioremap(offset, size) \
261 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
264 * ioremap_nocache - map bus memory into CPU space
265 * @offset: bus address of the memory
266 * @size: size of the resource to map
268 * ioremap_nocache performs a platform specific sequence of operations to
269 * make bus memory CPU accessible via the readb/readw/readl/writeb/
270 * writew/writel functions and the other mmio helpers. The returned
271 * address is not guaranteed to be usable directly as a virtual
274 * This version of ioremap ensures that the memory is marked uncachable
275 * on the CPU as well as honouring existing caching rules from things like
276 * the PCI bus. Note that there are other caches and buffers on many
277 * busses. In paticular driver authors should read up on PCI writes
279 * It's useful if some control registers are in such an area and
280 * write combining or read caching is not desirable:
282 #define ioremap_nocache(offset, size) \
283 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
286 * ioremap_cachable - map bus memory into CPU space
287 * @offset: bus address of the memory
288 * @size: size of the resource to map
290 * ioremap_nocache performs a platform specific sequence of operations to
291 * make bus memory CPU accessible via the readb/readw/readl/writeb/
292 * writew/writel functions and the other mmio helpers. The returned
293 * address is not guaranteed to be usable directly as a virtual
296 * This version of ioremap ensures that the memory is marked cachable by
297 * the CPU. Also enables full write-combining. Useful for some
298 * memory-like regions on I/O busses.
300 #define ioremap_cachable(offset, size) \
301 __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
304 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
305 * requests a cachable mapping, ioremap_uncached_accelerated requests a
306 * mapping using the uncached accelerated mode which isn't supported on
309 #define ioremap_cacheable_cow(offset, size) \
310 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
311 #define ioremap_uncached_accelerated(offset, size) \
312 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
314 static inline void iounmap(volatile void __iomem *addr)
316 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
318 if (cpu_has_64bit_addresses ||
319 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
327 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
329 static inline void pfx##write##bwlq(type val, \
330 volatile void __iomem *mem) \
332 volatile type *__mem; \
335 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
337 __val = pfx##ioswab##bwlq(val); \
339 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
341 else if (cpu_has_64bits) { \
342 unsigned long __flags; \
346 local_irq_save(__flags); \
347 __asm__ __volatile__( \
348 ".set mips3" "\t\t# __writeq""\n\t" \
349 "dsll32 %L0, %L0, 0" "\n\t" \
350 "dsrl32 %L0, %L0, 0" "\n\t" \
351 "dsll32 %M0, %M0, 0" "\n\t" \
352 "or %L0, %L0, %M0" "\n\t" \
353 "sd %L0, %2" "\n\t" \
356 : "0" (__val), "m" (*__mem)); \
358 local_irq_restore(__flags); \
363 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
365 volatile type *__mem; \
368 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
370 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
372 else if (cpu_has_64bits) { \
373 unsigned long __flags; \
376 local_irq_save(__flags); \
377 __asm__ __volatile__( \
378 ".set mips3" "\t\t# __readq" "\n\t" \
379 "ld %L0, %1" "\n\t" \
380 "dsra32 %M0, %L0, 0" "\n\t" \
381 "sll %L0, %L0, 0" "\n\t" \
386 local_irq_restore(__flags); \
392 return pfx##ioswab##bwlq(__val); \
395 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
397 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
399 volatile type *__addr; \
402 port = __swizzle_addr_##bwlq(port); \
403 __addr = (void *)(mips_io_port_base + port); \
405 __val = pfx##ioswab##bwlq(val); \
407 /* Really, we want this to be atomic */ \
408 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
414 static inline type pfx##in##bwlq##p(unsigned long port) \
416 volatile type *__addr; \
419 port = __swizzle_addr_##bwlq(port); \
420 __addr = (void *)(mips_io_port_base + port); \
422 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
427 return pfx##ioswab##bwlq(__val); \
430 #define __BUILD_MEMORY_PFX(bus, bwlq, type) \
432 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
434 #define BUILDIO_MEM(bwlq, type) \
436 __BUILD_MEMORY_PFX(__raw_, bwlq, type) \
437 __BUILD_MEMORY_PFX(, bwlq, type) \
438 __BUILD_MEMORY_PFX(__mem_, bwlq, type) \
445 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
446 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
447 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
449 #define BUILDIO_IOPORT(bwlq, type) \
450 __BUILD_IOPORT_PFX(, bwlq, type) \
451 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
453 BUILDIO_IOPORT(b, u8)
454 BUILDIO_IOPORT(w, u16)
455 BUILDIO_IOPORT(l, u32)
457 BUILDIO_IOPORT(q, u64)
460 #define __BUILDIO(bwlq, type) \
462 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
466 #define readb_relaxed readb
467 #define readw_relaxed readw
468 #define readl_relaxed readl
469 #define readq_relaxed readq
472 * Some code tests for these symbols
475 #define writeq writeq
477 #define __BUILD_MEMORY_STRING(bwlq, type) \
479 static inline void writes##bwlq(volatile void __iomem *mem, \
480 const void *addr, unsigned int count) \
482 const volatile type *__addr = addr; \
485 __mem_write##bwlq(*__addr, mem); \
490 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
491 unsigned int count) \
493 volatile type *__addr = addr; \
496 *__addr = __mem_read##bwlq(mem); \
501 #define __BUILD_IOPORT_STRING(bwlq, type) \
503 static inline void outs##bwlq(unsigned long port, const void *addr, \
504 unsigned int count) \
506 const volatile type *__addr = addr; \
509 __mem_out##bwlq(*__addr, port); \
514 static inline void ins##bwlq(unsigned long port, void *addr, \
515 unsigned int count) \
517 volatile type *__addr = addr; \
520 *__addr = __mem_in##bwlq(port); \
525 #define BUILDSTRING(bwlq, type) \
527 __BUILD_MEMORY_STRING(bwlq, type) \
528 __BUILD_IOPORT_STRING(bwlq, type)
538 /* Depends on MIPS II instruction set */
539 #define mmiowb() asm volatile ("sync" ::: "memory")
541 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
543 memset((void __force *) addr, val, count);
545 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
547 memcpy(dst, (void __force *) src, count);
549 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
551 memcpy((void __force *) dst, src, count);
557 #define ioread8(addr) readb(addr)
558 #define ioread16(addr) readw(addr)
559 #define ioread32(addr) readl(addr)
561 #define iowrite8(b,addr) writeb(b,addr)
562 #define iowrite16(w,addr) writew(w,addr)
563 #define iowrite32(l,addr) writel(l,addr)
565 #define ioread8_rep(a,b,c) readsb(a,b,c)
566 #define ioread16_rep(a,b,c) readsw(a,b,c)
567 #define ioread32_rep(a,b,c) readsl(a,b,c)
569 #define iowrite8_rep(a,b,c) writesb(a,b,c)
570 #define iowrite16_rep(a,b,c) writesw(a,b,c)
571 #define iowrite32_rep(a,b,c) writesl(a,b,c)
573 /* Create a virtual mapping cookie for an IO port range */
574 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
575 extern void ioport_unmap(void __iomem *);
577 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
579 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
580 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
583 * ISA space is 'always mapped' on currently supported MIPS systems, no need
584 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
585 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
586 * are physical addresses. The following constant pointer can be
587 * used as the IO-area pointer (it can be iounmapped as well, so the
588 * analogy with PCI is quite large):
590 #define __ISA_IO_base ((char *)(isa_slot_offset))
592 #define isa_readb(a) readb(__ISA_IO_base + (a))
593 #define isa_readw(a) readw(__ISA_IO_base + (a))
594 #define isa_readl(a) readl(__ISA_IO_base + (a))
595 #define isa_readq(a) readq(__ISA_IO_base + (a))
596 #define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
597 #define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
598 #define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
599 #define isa_writeq(q,a) writeq(q,__ISA_IO_base + (a))
600 #define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
601 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
602 #define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
605 * We don't have csum_partial_copy_fromio() yet, so we cheat here and
606 * just copy it. The net code will then do the checksum later.
608 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
609 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
612 * check_signature - find BIOS signatures
613 * @io_addr: mmio address to check
614 * @signature: signature block
615 * @length: length of signature
617 * Perform a signature comparison with the mmio address io_addr. This
618 * address should have been obtained by ioremap.
619 * Returns 1 on a match.
621 static inline int check_signature(char __iomem *io_addr,
622 const unsigned char *signature, int length)
626 if (readb(io_addr) != *signature)
638 * The caches on some architectures aren't dma-coherent and have need to
639 * handle this in software. There are three types of operations that
640 * can be applied to dma buffers.
642 * - dma_cache_wback_inv(start, size) makes caches and coherent by
643 * writing the content of the caches back to memory, if necessary.
644 * The function also invalidates the affected part of the caches as
645 * necessary before DMA transfers from outside to memory.
646 * - dma_cache_wback(start, size) makes caches and coherent by
647 * writing the content of the caches back to memory, if necessary.
648 * The function also invalidates the affected part of the caches as
649 * necessary before DMA transfers from outside to memory.
650 * - dma_cache_inv(start, size) invalidates the affected parts of the
651 * caches. Dirty lines of the caches may be written back or simply
652 * be discarded. This operation is necessary before dma operations
655 #ifdef CONFIG_DMA_NONCOHERENT
657 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
658 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
659 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
661 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size)
662 #define dma_cache_wback(start, size) _dma_cache_wback(start,size)
663 #define dma_cache_inv(start, size) _dma_cache_inv(start,size)
665 #else /* Sane hardware */
667 #define dma_cache_wback_inv(start,size) \
668 do { (void) (start); (void) (size); } while (0)
669 #define dma_cache_wback(start,size) \
670 do { (void) (start); (void) (size); } while (0)
671 #define dma_cache_inv(start,size) \
672 do { (void) (start); (void) (size); } while (0)
674 #endif /* CONFIG_DMA_NONCOHERENT */
677 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
678 * Avoid interrupt mucking, just adjust the address for 4-byte access.
679 * Assume the addresses are 8-byte aligned.
682 #define __CSR_32_ADJUST 4
684 #define __CSR_32_ADJUST 0
687 #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
688 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
691 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
694 #define xlate_dev_mem_ptr(p) __va(p)
697 * Convert a virtual cached pointer to an uncached pointer
699 #define xlate_dev_kmem_ptr(p) p
701 #endif /* _ASM_IO_H */