2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
9 #ifndef __ASM_CPU_FEATURES_H
10 #define __ASM_CPU_FEATURES_H
12 #include <linux/config.h>
15 #include <asm/cpu-info.h>
16 #include <cpu-feature-overrides.h>
19 * SMP assumption: Options of CPU 0 are a superset of all processors.
20 * This is true for all known MIPS systems.
23 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
26 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
29 #define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
32 #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
35 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
37 #ifndef cpu_has_counter
38 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
41 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
44 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
47 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
49 #ifndef cpu_has_cache_cdex_p
50 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
52 #ifndef cpu_has_cache_cdex_s
53 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
55 #ifndef cpu_has_prefetch
56 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
58 #ifndef cpu_has_mcheck
59 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
62 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
65 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
67 #ifndef cpu_has_mips16
68 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
71 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
73 #ifndef cpu_has_mips3d
74 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
76 #ifndef cpu_has_smartmips
77 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
79 #ifndef cpu_has_vtag_icache
80 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
82 #ifndef cpu_has_dc_aliases
83 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
85 #ifndef cpu_has_ic_fills_f_dc
86 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
90 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
91 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
92 * don't. For maintaining I-cache coherency this means we need to flush the
93 * D-cache all the way back to whever the I-cache does refills from, so the
94 * I-cache has a chance to see the new data at all. Then we have to flush the
96 * Note we may have been rescheduled and may no longer be running on the CPU
97 * that did the store so we can't optimize this into only doing the flush on
100 #ifndef cpu_icache_snoops_remote_store
102 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
104 #define cpu_icache_snoops_remote_store 1
109 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
113 * Certain CPUs may throw bizarre exceptions if not the whole cacheline
114 * contains valid instructions. For these we ensure proper alignment of
115 * signal trampolines and pad them to the size of a full cache lines with
116 * nops. This is also used in structure definitions so can't be a test macro
119 #ifndef PLAT_TRAMPOLINE_STUFF_LINE
120 #define PLAT_TRAMPOLINE_STUFF_LINE 0UL
124 # ifndef cpu_has_nofpuex
125 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
127 # ifndef cpu_has_64bits
128 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
130 # ifndef cpu_has_64bit_zero_reg
131 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
133 # ifndef cpu_has_64bit_gp_regs
134 # define cpu_has_64bit_gp_regs 0
136 # ifndef cpu_has_64bit_addresses
137 # define cpu_has_64bit_addresses 0
142 # ifndef cpu_has_nofpuex
143 # define cpu_has_nofpuex 0
145 # ifndef cpu_has_64bits
146 # define cpu_has_64bits 1
148 # ifndef cpu_has_64bit_zero_reg
149 # define cpu_has_64bit_zero_reg 1
151 # ifndef cpu_has_64bit_gp_regs
152 # define cpu_has_64bit_gp_regs 1
154 # ifndef cpu_has_64bit_addresses
155 # define cpu_has_64bit_addresses 1
159 #ifndef cpu_has_subset_pcaches
160 #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
163 #ifndef cpu_dcache_line_size
164 #define cpu_dcache_line_size() current_cpu_data.dcache.linesz
166 #ifndef cpu_icache_line_size
167 #define cpu_icache_line_size() current_cpu_data.icache.linesz
169 #ifndef cpu_scache_line_size
170 #define cpu_scache_line_size() current_cpu_data.scache.linesz
173 #endif /* __ASM_CPU_FEATURES_H */