1 #ifndef _ASM_M32R_SYSTEM_H
2 #define _ASM_M32R_SYSTEM_H
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
9 * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
10 * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
13 #include <linux/compiler.h>
14 #include <asm/assembler.h>
19 * switch_to(prev, next) should switch from task `prev' to `next'
20 * `prev' will never be the same as `next'.
22 * `next' and `prev' should be struct task_struct, but it isn't always defined
25 #if defined(CONFIG_FRAME_POINTER) || \
26 !defined(CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER)
27 #define M32R_PUSH_FP " push fp\n"
28 #define M32R_POP_FP " pop fp\n"
30 #define M32R_PUSH_FP ""
31 #define M32R_POP_FP ""
34 #define switch_to(prev, next, last) do { \
35 __asm__ __volatile__ ( \
36 " seth lr, #high(1f) \n" \
37 " or3 lr, lr, #low(1f) \n" \
38 " st lr, @%4 ; store old LR \n" \
39 " ld lr, @%5 ; load new LR \n" \
41 " st sp, @%2 ; store old SP \n" \
42 " ld sp, @%3 ; load new SP \n" \
43 " push %1 ; store `prev' on new stack \n" \
47 " pop %0 ; restore `__last' from new stack \n" \
51 "r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \
52 "r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \
57 /* Interrupt Control */
58 #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
59 #define local_irq_enable() \
60 __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
61 #define local_irq_disable() \
62 __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
63 #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
64 static inline void local_irq_enable(void)
69 "or3 %0, %0, #0x0040; \n\t"
71 : "=&r" (tmpreg) : : "cbit", "memory");
74 static inline void local_irq_disable(void)
76 unsigned long tmpreg0, tmpreg1;
78 "ld24 %0, #0 ; Use 32-bit insn. \n\t"
79 "mvfc %1, psw ; No interrupt can be accepted here. \n\t"
81 "and3 %0, %1, #0xffbf \n\t"
83 : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
85 #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
87 #define local_save_flags(x) \
88 __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
90 #define local_irq_restore(x) \
91 __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
92 : "r" (x) : "cbit", "memory")
94 #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
95 #define local_irq_save(x) \
96 __asm__ __volatile__( \
97 "mvfc %0, psw; \n\t" \
98 "clrpsw #0x40 -> nop; \n\t" \
99 : "=r" (x) : /* no input */ : "memory")
100 #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
101 #define local_irq_save(x) \
103 unsigned long tmpreg; \
104 __asm__ __volatile__( \
106 "mvfc %0, psw \n\t" \
107 "mvtc %1, psw \n\t" \
108 "and3 %1, %0, #0xffbf \n\t" \
109 "mvtc %1, psw \n\t" \
110 : "=r" (x), "=&r" (tmpreg) \
111 : : "cbit", "memory"); \
113 #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
115 #define irqs_disabled() \
117 unsigned long flags; \
118 local_save_flags(flags); \
122 #define nop() __asm__ __volatile__ ("nop" : : )
124 #define xchg(ptr, x) \
125 ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
126 #define xchg_local(ptr, x) \
127 ((__typeof__(*(ptr)))__xchg_local((unsigned long)(x), (ptr), \
131 extern void __xchg_called_with_bad_pointer(void);
134 #ifdef CONFIG_CHIP_M32700_TS1
135 #define DCACHE_CLEAR(reg0, reg1, addr) \
136 "seth "reg1", #high(dcache_dummy); \n\t" \
137 "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
138 "lock "reg0", @"reg1"; \n\t" \
139 "add3 "reg0", "addr", #0x1000; \n\t" \
140 "ld "reg0", @"reg0"; \n\t" \
141 "add3 "reg0", "addr", #0x2000; \n\t" \
142 "ld "reg0", @"reg0"; \n\t" \
143 "unlock "reg0", @"reg1"; \n\t"
144 /* FIXME: This workaround code cannot handle kernel modules
145 * correctly under SMP environment.
147 #else /* CONFIG_CHIP_M32700_TS1 */
148 #define DCACHE_CLEAR(reg0, reg1, addr)
149 #endif /* CONFIG_CHIP_M32700_TS1 */
151 static __always_inline unsigned long
152 __xchg(unsigned long x, volatile void *ptr, int size)
155 unsigned long tmp = 0;
157 local_irq_save(flags);
162 __asm__ __volatile__ (
165 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
168 __asm__ __volatile__ (
171 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
174 __asm__ __volatile__ (
177 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
179 #else /* CONFIG_SMP */
181 __asm__ __volatile__ (
182 DCACHE_CLEAR("%0", "r4", "%2")
184 "unlock %1, @%2; \n\t"
185 : "=&r" (tmp) : "r" (x), "r" (ptr)
187 #ifdef CONFIG_CHIP_M32700_TS1
189 #endif /* CONFIG_CHIP_M32700_TS1 */
193 __xchg_called_with_bad_pointer();
194 #endif /* CONFIG_SMP */
197 local_irq_restore(flags);
202 static __always_inline unsigned long
203 __xchg_local(unsigned long x, volatile void *ptr, int size)
206 unsigned long tmp = 0;
208 local_irq_save(flags);
212 __asm__ __volatile__ (
215 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
218 __asm__ __volatile__ (
221 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
224 __asm__ __volatile__ (
227 : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
230 __xchg_called_with_bad_pointer();
233 local_irq_restore(flags);
238 #define __HAVE_ARCH_CMPXCHG 1
240 static inline unsigned long
241 __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
246 local_irq_save(flags);
247 __asm__ __volatile__ (
248 DCACHE_CLEAR("%0", "r4", "%1")
249 M32R_LOCK" %0, @%1; \n"
250 " bne %0, %2, 1f; \n"
251 M32R_UNLOCK" %3, @%1; \n"
255 M32R_UNLOCK" %0, @%1; \n"
259 : "r" (p), "r" (old), "r" (new)
261 #ifdef CONFIG_CHIP_M32700_TS1
263 #endif /* CONFIG_CHIP_M32700_TS1 */
265 local_irq_restore(flags);
270 static inline unsigned long
271 __cmpxchg_local_u32(volatile unsigned int *p, unsigned int old,
277 local_irq_save(flags);
278 __asm__ __volatile__ (
279 DCACHE_CLEAR("%0", "r4", "%1")
281 " bne %0, %2, 1f; \n"
290 : "r" (p), "r" (old), "r" (new)
292 #ifdef CONFIG_CHIP_M32700_TS1
294 #endif /* CONFIG_CHIP_M32700_TS1 */
296 local_irq_restore(flags);
301 /* This function doesn't exist, so you'll get a linker error
302 if something tries to do an invalid cmpxchg(). */
303 extern void __cmpxchg_called_with_bad_pointer(void);
305 static inline unsigned long
306 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
310 return __cmpxchg_u32(ptr, old, new);
311 #if 0 /* we don't have __cmpxchg_u64 */
313 return __cmpxchg_u64(ptr, old, new);
316 __cmpxchg_called_with_bad_pointer();
320 #define cmpxchg(ptr, o, n) \
321 ((__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)(o), \
322 (unsigned long)(n), sizeof(*(ptr))))
324 #include <asm-generic/cmpxchg-local.h>
326 static inline unsigned long __cmpxchg_local(volatile void *ptr,
328 unsigned long new, int size)
332 return __cmpxchg_local_u32(ptr, old, new);
334 return __cmpxchg_local_generic(ptr, old, new, size);
341 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
344 #define cmpxchg_local(ptr, o, n) \
345 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
346 (unsigned long)(n), sizeof(*(ptr))))
347 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
349 #endif /* __KERNEL__ */
354 * mb() prevents loads and stores being reordered across this point.
355 * rmb() prevents loads being reordered across this point.
356 * wmb() prevents stores being reordered across this point.
358 #define mb() barrier()
363 * read_barrier_depends - Flush all pending reads that subsequents reads
366 * No data-dependent reads from memory-like regions are ever reordered
367 * over this barrier. All reads preceding this primitive are guaranteed
368 * to access memory (but not necessarily other CPUs' caches) before any
369 * reads following this primitive that depend on the data return by
370 * any of the preceding reads. This primitive is much lighter weight than
371 * rmb() on most CPUs, and is never heavier weight than is
374 * These ordering constraints are respected by both the local CPU
377 * Ordering is not guaranteed by anything other than these primitives,
378 * not even by data dependencies. See the documentation for
379 * memory_barrier() for examples and URLs to more information.
381 * For example, the following code would force ordering (the initial
382 * value of "a" is zero, "b" is one, and "p" is "&a"):
390 * read_barrier_depends();
395 * because the read of "*q" depends on the read of "p" and these
396 * two reads are separated by a read_barrier_depends(). However,
397 * the following code, with the same initial values for "a" and "b":
405 * read_barrier_depends();
409 * does not enforce ordering, since there is no data dependency between
410 * the read of "a" and the read of "b". Therefore, on some CPUs, such
411 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
412 * in cases like this where there are no data dependencies.
415 #define read_barrier_depends() do { } while (0)
418 #define smp_mb() mb()
419 #define smp_rmb() rmb()
420 #define smp_wmb() wmb()
421 #define smp_read_barrier_depends() read_barrier_depends()
422 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
424 #define smp_mb() barrier()
425 #define smp_rmb() barrier()
426 #define smp_wmb() barrier()
427 #define smp_read_barrier_depends() do { } while (0)
428 #define set_mb(var, value) do { var = value; barrier(); } while (0)
431 #define arch_align_stack(x) (x)
433 #endif /* _ASM_M32R_SYSTEM_H */