err.no Git - linux-2.6/blob - include/asm-i386/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <linux/config.h>
   8 #include <linux/compiler.h>
   9
  10 /*
  11  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  12  *
  13  * Simple spin lock operations.  There are two variants, one clears IRQ's
  14  * on the local processor, one does not.
  15  *
  16  * We make no fairness assumptions. They have a cost.
  17  *
  18  * (the type definitions are in asm/spinlock_types.h)
  19  */
  20
  21 #define __raw_spin_is_locked(x) \
  22                 (*(volatile signed char *)(&(x)->slock) <= 0)
  23
  24 #define __raw_spin_lock_string \
  25         "\n1:\t" \
  26         "lock ; decb %0\n\t" \
  27         "jns 3f\n" \
  28         "2:\t" \
  29         "rep;nop\n\t" \
  30         "cmpb $0,%0\n\t" \
  31         "jle 2b\n\t" \
  32         "jmp 1b\n" \
  33         "3:\n\t"
  34
  35 #define __raw_spin_lock_string_flags \
  36         "\n1:\t" \
  37         "lock ; decb %0\n\t" \
  38         "jns 4f\n\t" \
  39         "2:\t" \
  40         "testl $0x200, %1\n\t" \
  41         "jz 3f\n\t" \
  42         "sti\n\t" \
  43         "3:\t" \
  44         "rep;nop\n\t" \
  45         "cmpb $0, %0\n\t" \
  46         "jle 3b\n\t" \
  47         "cli\n\t" \
  48         "jmp 1b\n" \
  49         "4:\n\t"
  50
  51 #define __raw_spin_lock_string_up \
  52         "\n\tdecb %0"
  53
  54 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  55 {
  56         alternative_smp(
  57                 __raw_spin_lock_string,
  58                 __raw_spin_lock_string_up,
  59                 "=m" (lock->slock) : : "memory");
  60 }
  61
  62 static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
  63 {
  64         alternative_smp(
  65                 __raw_spin_lock_string_flags,
  66                 __raw_spin_lock_string_up,
  67                 "=m" (lock->slock) : "r" (flags) : "memory");
  68 }
  69
  70 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  71 {
  72         char oldval;
  73         __asm__ __volatile__(
  74                 "xchgb %b0,%1"
  75                 :"=q" (oldval), "=m" (lock->slock)
  76                 :"0" (0) : "memory");
  77         return oldval > 0;
  78 }
  79
  80 /*
  81  * __raw_spin_unlock based on writing $1 to the low byte.
  82  * This method works. Despite all the confusion.
  83  * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
  84  * (PPro errata 66, 92)
  85  */
  86
  87 #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
  88
  89 #define __raw_spin_unlock_string \
  90         "movb $1,%0" \
  91                 :"=m" (lock->slock) : : "memory"
  92
  93
  94 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  95 {
  96         __asm__ __volatile__(
  97                 __raw_spin_unlock_string
  98         );
  99 }
 100
 101 #else
 102
 103 #define __raw_spin_unlock_string \
 104         "xchgb %b0, %1" \
 105                 :"=q" (oldval), "=m" (lock->slock) \
 106                 :"0" (oldval) : "memory"
 107
 108 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 109 {
 110         char oldval = 1;
 111
 112         __asm__ __volatile__(
 113                 __raw_spin_unlock_string
 114         );
 115 }
 116
 117 #endif
 118
 119 #define __raw_spin_unlock_wait(lock) \
 120         do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
 121
 122 /*
 123  * Read-write spinlocks, allowing multiple readers
 124  * but only one writer.
 125  *
 126  * NOTE! it is quite common to have readers in interrupts
 127  * but no interrupt writers. For those circumstances we
 128  * can "mix" irq-safe locks - any writer needs to get a
 129  * irq-safe write-lock, but readers can get non-irqsafe
 130  * read-locks.
 131  *
 132  * On x86, we implement read-write locks as a 32-bit counter
 133  * with the high bit (sign) being the "contended" bit.
 134  *
 135  * The inline assembly is non-obvious. Think about it.
 136  *
 137  * Changed to use the same technique as rw semaphores.  See
 138  * semaphore.h for details.  -ben
 139  *
 140  * the helpers are in arch/i386/kernel/semaphore.c
 141  */
 142
 143 /**
 144  * read_can_lock - would read_trylock() succeed?
 145  * @lock: the rwlock in question.
 146  */
 147 #define __raw_read_can_lock(x)          ((int)(x)->lock > 0)
 148
 149 /**
 150  * write_can_lock - would write_trylock() succeed?
 151  * @lock: the rwlock in question.
 152  */
 153 #define __raw_write_can_lock(x)         ((x)->lock == RW_LOCK_BIAS)
 154
 155 static inline void __raw_read_lock(raw_rwlock_t *rw)
 156 {
 157         __build_read_lock(rw, "__read_lock_failed");
 158 }
 159
 160 static inline void __raw_write_lock(raw_rwlock_t *rw)
 161 {
 162         __build_write_lock(rw, "__write_lock_failed");
 163 }
 164
 165 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 166 {
 167         atomic_t *count = (atomic_t *)lock;
 168         atomic_dec(count);
 169         if (atomic_read(count) >= 0)
 170                 return 1;
 171         atomic_inc(count);
 172         return 0;
 173 }
 174
 175 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 176 {
 177         atomic_t *count = (atomic_t *)lock;
 178         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 179                 return 1;
 180         atomic_add(RW_LOCK_BIAS, count);
 181         return 0;
 182 }
 183
 184 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 185 {
 186         asm volatile(LOCK_PREFIX "incl %0" :"=m" (rw->lock) : : "memory");
 187 }
 188
 189 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 190 {
 191         asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ", %0"
 192                                  : "=m" (rw->lock) : : "memory");
 193 }
 194
 195 #endif /* __ASM_SPINLOCK_H */