err.no Git - linux-2.6/blob - include/asm-i386/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <linux/compiler.h>
   8
   9 /*
  10  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  11  *
  12  * Simple spin lock operations.  There are two variants, one clears IRQ's
  13  * on the local processor, one does not.
  14  *
  15  * We make no fairness assumptions. They have a cost.
  16  *
  17  * (the type definitions are in asm/spinlock_types.h)
  18  */
  19
  20 #define __raw_spin_is_locked(x) \
  21                 (*(volatile signed char *)(&(x)->slock) <= 0)
  22
  23 #define __raw_spin_lock_string \
  24         "\n1:\t" \
  25         "lock ; decb %0\n\t" \
  26         "jns 3f\n" \
  27         "2:\t" \
  28         "rep;nop\n\t" \
  29         "cmpb $0,%0\n\t" \
  30         "jle 2b\n\t" \
  31         "jmp 1b\n" \
  32         "3:\n\t"
  33
  34 /*
  35  * NOTE: there's an irqs-on section here, which normally would have to be
  36  * irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use
  37  * __raw_spin_lock_string_flags().
  38  */
  39 #define __raw_spin_lock_string_flags \
  40         "\n1:\t" \
  41         "lock ; decb %0\n\t" \
  42         "jns 5f\n" \
  43         "2:\t" \
  44         "testl $0x200, %1\n\t" \
  45         "jz 4f\n\t" \
  46         "sti\n" \
  47         "3:\t" \
  48         "rep;nop\n\t" \
  49         "cmpb $0, %0\n\t" \
  50         "jle 3b\n\t" \
  51         "cli\n\t" \
  52         "jmp 1b\n" \
  53         "4:\t" \
  54         "rep;nop\n\t" \
  55         "cmpb $0, %0\n\t" \
  56         "jg 1b\n\t" \
  57         "jmp 4b\n" \
  58         "5:\n\t"
  59
  60 #define __raw_spin_lock_string_up \
  61         "\n\tdecb %0"
  62
  63 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  64 {
  65         alternative_smp(
  66                 __raw_spin_lock_string,
  67                 __raw_spin_lock_string_up,
  68                 "=m" (lock->slock) : : "memory");
  69 }
  70
  71 static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
  72 {
  73         alternative_smp(
  74                 __raw_spin_lock_string_flags,
  75                 __raw_spin_lock_string_up,
  76                 "=m" (lock->slock) : "r" (flags) : "memory");
  77 }
  78
  79 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  80 {
  81         char oldval;
  82         __asm__ __volatile__(
  83                 "xchgb %b0,%1"
  84                 :"=q" (oldval), "=m" (lock->slock)
  85                 :"0" (0) : "memory");
  86         return oldval > 0;
  87 }
  88
  89 /*
  90  * __raw_spin_unlock based on writing $1 to the low byte.
  91  * This method works. Despite all the confusion.
  92  * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
  93  * (PPro errata 66, 92)
  94  */
  95
  96 #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
  97
  98 #define __raw_spin_unlock_string \
  99         "movb $1,%0" \
 100                 :"=m" (lock->slock) : : "memory"
 101
 102
 103 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 104 {
 105         __asm__ __volatile__(
 106                 __raw_spin_unlock_string
 107         );
 108 }
 109
 110 #else
 111
 112 #define __raw_spin_unlock_string \
 113         "xchgb %b0, %1" \
 114                 :"=q" (oldval), "=m" (lock->slock) \
 115                 :"0" (oldval) : "memory"
 116
 117 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 118 {
 119         char oldval = 1;
 120
 121         __asm__ __volatile__(
 122                 __raw_spin_unlock_string
 123         );
 124 }
 125
 126 #endif
 127
 128 #define __raw_spin_unlock_wait(lock) \
 129         do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
 130
 131 /*
 132  * Read-write spinlocks, allowing multiple readers
 133  * but only one writer.
 134  *
 135  * NOTE! it is quite common to have readers in interrupts
 136  * but no interrupt writers. For those circumstances we
 137  * can "mix" irq-safe locks - any writer needs to get a
 138  * irq-safe write-lock, but readers can get non-irqsafe
 139  * read-locks.
 140  *
 141  * On x86, we implement read-write locks as a 32-bit counter
 142  * with the high bit (sign) being the "contended" bit.
 143  *
 144  * The inline assembly is non-obvious. Think about it.
 145  *
 146  * Changed to use the same technique as rw semaphores.  See
 147  * semaphore.h for details.  -ben
 148  *
 149  * the helpers are in arch/i386/kernel/semaphore.c
 150  */
 151
 152 /**
 153  * read_can_lock - would read_trylock() succeed?
 154  * @lock: the rwlock in question.
 155  */
 156 #define __raw_read_can_lock(x)          ((int)(x)->lock > 0)
 157
 158 /**
 159  * write_can_lock - would write_trylock() succeed?
 160  * @lock: the rwlock in question.
 161  */
 162 #define __raw_write_can_lock(x)         ((x)->lock == RW_LOCK_BIAS)
 163
 164 static inline void __raw_read_lock(raw_rwlock_t *rw)
 165 {
 166         __build_read_lock(rw, "__read_lock_failed");
 167 }
 168
 169 static inline void __raw_write_lock(raw_rwlock_t *rw)
 170 {
 171         __build_write_lock(rw, "__write_lock_failed");
 172 }
 173
 174 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 175 {
 176         atomic_t *count = (atomic_t *)lock;
 177         atomic_dec(count);
 178         if (atomic_read(count) >= 0)
 179                 return 1;
 180         atomic_inc(count);
 181         return 0;
 182 }
 183
 184 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 185 {
 186         atomic_t *count = (atomic_t *)lock;
 187         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 188                 return 1;
 189         atomic_add(RW_LOCK_BIAS, count);
 190         return 0;
 191 }
 192
 193 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 194 {
 195         asm volatile(LOCK_PREFIX "incl %0" :"=m" (rw->lock) : : "memory");
 196 }
 197
 198 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 199 {
 200         asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ", %0"
 201                                  : "=m" (rw->lock) : : "memory");
 202 }
 203
 204 #endif /* __ASM_SPINLOCK_H */