2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/config.h>
21 #include <linux/threads.h>
22 #include <asm/percpu.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
31 #define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
63 int x86_cache_alignment; /* In bytes */
69 unsigned long loops_per_jiffy;
70 unsigned char x86_max_cores; /* cpuid returned max cores value */
71 unsigned char booted_cores; /* number of cores as seen by OS */
73 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
75 #define X86_VENDOR_INTEL 0
76 #define X86_VENDOR_CYRIX 1
77 #define X86_VENDOR_AMD 2
78 #define X86_VENDOR_UMC 3
79 #define X86_VENDOR_NEXGEN 4
80 #define X86_VENDOR_CENTAUR 5
81 #define X86_VENDOR_RISE 6
82 #define X86_VENDOR_TRANSMETA 7
83 #define X86_VENDOR_NSC 8
84 #define X86_VENDOR_NUM 9
85 #define X86_VENDOR_UNKNOWN 0xff
88 * capabilities of CPUs
91 extern struct cpuinfo_x86 boot_cpu_data;
92 extern struct cpuinfo_x86 new_cpu_data;
93 extern struct tss_struct doublefault_tss;
94 DECLARE_PER_CPU(struct tss_struct, init_tss);
97 extern struct cpuinfo_x86 cpu_data[];
98 #define current_cpu_data cpu_data[smp_processor_id()]
100 #define cpu_data (&boot_cpu_data)
101 #define current_cpu_data boot_cpu_data
104 extern int phys_proc_id[NR_CPUS];
105 extern int cpu_core_id[NR_CPUS];
106 extern char ignore_fpu_irq;
108 extern void identify_cpu(struct cpuinfo_x86 *);
109 extern void print_cpu_info(struct cpuinfo_x86 *);
110 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
113 extern void detect_ht(struct cpuinfo_x86 *c);
115 static inline void detect_ht(struct cpuinfo_x86 *c) {}
121 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
122 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
123 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
124 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
125 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
126 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
127 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
128 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
129 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
130 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
131 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
132 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
133 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
134 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
135 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
136 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
137 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
140 * Generic CPUID function
141 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
142 * resulting in stale register contents being returned.
144 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
154 /* Some CPUID calls want 'count' to be placed in ecx */
155 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
163 : "0" (op), "c" (count));
167 * CPUID functions returning a single datum
169 static inline unsigned int cpuid_eax(unsigned int op)
179 static inline unsigned int cpuid_ebx(unsigned int op)
181 unsigned int eax, ebx;
184 : "=a" (eax), "=b" (ebx)
189 static inline unsigned int cpuid_ecx(unsigned int op)
191 unsigned int eax, ecx;
194 : "=a" (eax), "=c" (ecx)
199 static inline unsigned int cpuid_edx(unsigned int op)
201 unsigned int eax, edx;
204 : "=a" (eax), "=d" (edx)
210 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
213 * Intel CPU features in CR4
215 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
216 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
217 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
218 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
219 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
220 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
221 #define X86_CR4_MCE 0x0040 /* Machine check enable */
222 #define X86_CR4_PGE 0x0080 /* enable global pages */
223 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
224 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
225 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
228 * Save the cr4 feature set we're using (ie
229 * Pentium 4MB enable and PPro Global page
230 * enable), so that any CPU's that boot up
231 * after us can get the correct flags.
233 extern unsigned long mmu_cr4_features;
235 static inline void set_in_cr4 (unsigned long mask)
238 mmu_cr4_features |= mask;
244 static inline void clear_in_cr4 (unsigned long mask)
247 mmu_cr4_features &= ~mask;
254 * NSC/Cyrix CPU configuration register indexes
257 #define CX86_PCR0 0x20
258 #define CX86_GCR 0xb8
259 #define CX86_CCR0 0xc0
260 #define CX86_CCR1 0xc1
261 #define CX86_CCR2 0xc2
262 #define CX86_CCR3 0xc3
263 #define CX86_CCR4 0xe8
264 #define CX86_CCR5 0xe9
265 #define CX86_CCR6 0xea
266 #define CX86_CCR7 0xeb
267 #define CX86_PCR1 0xf0
268 #define CX86_DIR0 0xfe
269 #define CX86_DIR1 0xff
270 #define CX86_ARR_BASE 0xc4
271 #define CX86_RCR_BASE 0xdc
274 * NSC/Cyrix CPU indexed register access macros
277 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
279 #define setCx86(reg, data) do { \
281 outb((data), 0x23); \
284 static inline void serialize_cpu(void)
286 __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
289 static inline void __monitor(const void *eax, unsigned long ecx,
292 /* "monitor %eax,%ecx,%edx;" */
294 ".byte 0x0f,0x01,0xc8;"
295 : :"a" (eax), "c" (ecx), "d"(edx));
298 static inline void __mwait(unsigned long eax, unsigned long ecx)
300 /* "mwait %eax,%ecx;" */
302 ".byte 0x0f,0x01,0xc9;"
303 : :"a" (eax), "c" (ecx));
306 /* from system description table in BIOS. Mostly for MCA use, but
307 others may find it useful. */
308 extern unsigned int machine_id;
309 extern unsigned int machine_submodel_id;
310 extern unsigned int BIOS_revision;
311 extern unsigned int mca_pentium_flag;
313 /* Boot loader type from the setup header */
314 extern int bootloader_type;
317 * User space process size: 3GB (default).
319 #define TASK_SIZE (PAGE_OFFSET)
321 /* This decides where the kernel will search for a free chunk of vm
322 * space during mmap's.
324 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
326 #define HAVE_ARCH_PICK_MMAP_LAYOUT
331 #define IO_BITMAP_BITS 65536
332 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
333 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
334 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
335 #define INVALID_IO_BITMAP_OFFSET 0x8000
336 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
338 struct i387_fsave_struct {
346 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
347 long status; /* software status information */
350 struct i387_fxsave_struct {
361 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
362 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
364 } __attribute__ ((aligned (16)));
366 struct i387_soft_struct {
374 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
375 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
377 unsigned long entry_eip;
381 struct i387_fsave_struct fsave;
382 struct i387_fxsave_struct fxsave;
383 struct i387_soft_struct soft;
390 struct thread_struct;
393 unsigned short back_link,__blh;
395 unsigned short ss0,__ss0h;
397 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
399 unsigned short ss2,__ss2h;
402 unsigned long eflags;
403 unsigned long eax,ecx,edx,ebx;
408 unsigned short es, __esh;
409 unsigned short cs, __csh;
410 unsigned short ss, __ssh;
411 unsigned short ds, __dsh;
412 unsigned short fs, __fsh;
413 unsigned short gs, __gsh;
414 unsigned short ldt, __ldth;
415 unsigned short trace, io_bitmap_base;
417 * The extra 1 is there because the CPU will access an
418 * additional byte beyond the end of the IO permission
419 * bitmap. The extra byte must be all 1 bits, and must
420 * be within the limit.
422 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
424 * Cache the current maximum and the last task that used the bitmap:
426 unsigned long io_bitmap_max;
427 struct thread_struct *io_bitmap_owner;
429 * pads the TSS to be cacheline-aligned (size is 0x100)
431 unsigned long __cacheline_filler[35];
433 * .. and then another 0x100 bytes for emergency kernel stack
435 unsigned long stack[64];
436 } __attribute__((packed));
438 #define ARCH_MIN_TASKALIGN 16
440 struct thread_struct {
441 /* cached TLS descriptors. */
442 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
444 unsigned long sysenter_cs;
449 /* Hardware debugging registers */
450 unsigned long debugreg[8]; /* %%db0-7 debug registers */
452 unsigned long cr2, trap_no, error_code;
453 /* floating point info */
454 union i387_union i387;
455 /* virtual 86 mode info */
456 struct vm86_struct __user * vm86_info;
457 unsigned long screen_bitmap;
458 unsigned long v86flags, v86mask, saved_esp0;
459 unsigned int saved_fs, saved_gs;
461 unsigned long *io_bitmap_ptr;
463 /* max allowed port in the bitmap, in bytes: */
464 unsigned long io_bitmap_max;
467 #define INIT_THREAD { \
469 .sysenter_cs = __KERNEL_CS, \
470 .io_bitmap_ptr = NULL, \
474 * Note that the .io_bitmap member must be extra-big. This is because
475 * the CPU will access an additional byte beyond the end of the IO
476 * permission bitmap. The extra byte must be all 1 bits, and must
477 * be within the limit.
480 .esp0 = sizeof(init_stack) + (long)&init_stack, \
481 .ss0 = __KERNEL_DS, \
482 .ss1 = __KERNEL_CS, \
483 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
484 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
487 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
489 tss->esp0 = thread->esp0;
490 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
491 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
492 tss->ss1 = thread->sysenter_cs;
493 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
497 #define start_thread(regs, new_eip, new_esp) do { \
498 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
500 regs->xds = __USER_DS; \
501 regs->xes = __USER_DS; \
502 regs->xss = __USER_DS; \
503 regs->xcs = __USER_CS; \
504 regs->eip = new_eip; \
505 regs->esp = new_esp; \
509 * These special macros can be used to get or set a debugging register
511 #define get_debugreg(var, register) \
512 __asm__("movl %%db" #register ", %0" \
514 #define set_debugreg(value, register) \
515 __asm__("movl %0,%%db" #register \
520 * Set IOPL bits in EFLAGS from given mask
522 static inline void set_iopl_mask(unsigned mask)
525 __asm__ __volatile__ ("pushfl;"
532 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
535 /* Forward declaration, a strange C thing */
539 /* Free all resources held by a thread. */
540 extern void release_thread(struct task_struct *);
542 /* Prepare to copy thread state - unlazy all lazy status */
543 extern void prepare_to_copy(struct task_struct *tsk);
546 * create a kernel thread without removing it from tasklists
548 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
550 extern unsigned long thread_saved_pc(struct task_struct *tsk);
551 void show_trace(struct task_struct *task, unsigned long *stack);
553 unsigned long get_wchan(struct task_struct *p);
555 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
556 #define KSTK_TOP(info) \
558 unsigned long *__ptr = (unsigned long *)(info); \
559 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
562 #define task_pt_regs(task) \
564 struct pt_regs *__regs__; \
565 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
569 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
570 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
573 struct microcode_header {
581 unsigned int datasize;
582 unsigned int totalsize;
583 unsigned int reserved[3];
587 struct microcode_header hdr;
588 unsigned int bits[0];
591 typedef struct microcode microcode_t;
592 typedef struct microcode_header microcode_header_t;
594 /* microcode format is extended from prescott processors */
595 struct extended_signature {
601 struct extended_sigtable {
604 unsigned int reserved[3];
605 struct extended_signature sigs[0];
607 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
608 #define MICROCODE_IOCFREE _IO('6',0)
610 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
611 static inline void rep_nop(void)
613 __asm__ __volatile__("rep;nop": : :"memory");
616 #define cpu_relax() rep_nop()
618 /* generic versions from gas */
619 #define GENERIC_NOP1 ".byte 0x90\n"
620 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
621 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
622 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
623 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
624 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
625 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
626 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
629 #define K8_NOP1 GENERIC_NOP1
630 #define K8_NOP2 ".byte 0x66,0x90\n"
631 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
632 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
633 #define K8_NOP5 K8_NOP3 K8_NOP2
634 #define K8_NOP6 K8_NOP3 K8_NOP3
635 #define K8_NOP7 K8_NOP4 K8_NOP3
636 #define K8_NOP8 K8_NOP4 K8_NOP4
639 /* uses eax dependencies (arbitary choice) */
640 #define K7_NOP1 GENERIC_NOP1
641 #define K7_NOP2 ".byte 0x8b,0xc0\n"
642 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
643 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
644 #define K7_NOP5 K7_NOP4 ASM_NOP1
645 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
646 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
647 #define K7_NOP8 K7_NOP7 ASM_NOP1
650 #define ASM_NOP1 K8_NOP1
651 #define ASM_NOP2 K8_NOP2
652 #define ASM_NOP3 K8_NOP3
653 #define ASM_NOP4 K8_NOP4
654 #define ASM_NOP5 K8_NOP5
655 #define ASM_NOP6 K8_NOP6
656 #define ASM_NOP7 K8_NOP7
657 #define ASM_NOP8 K8_NOP8
658 #elif defined(CONFIG_MK7)
659 #define ASM_NOP1 K7_NOP1
660 #define ASM_NOP2 K7_NOP2
661 #define ASM_NOP3 K7_NOP3
662 #define ASM_NOP4 K7_NOP4
663 #define ASM_NOP5 K7_NOP5
664 #define ASM_NOP6 K7_NOP6
665 #define ASM_NOP7 K7_NOP7
666 #define ASM_NOP8 K7_NOP8
668 #define ASM_NOP1 GENERIC_NOP1
669 #define ASM_NOP2 GENERIC_NOP2
670 #define ASM_NOP3 GENERIC_NOP3
671 #define ASM_NOP4 GENERIC_NOP4
672 #define ASM_NOP5 GENERIC_NOP5
673 #define ASM_NOP6 GENERIC_NOP6
674 #define ASM_NOP7 GENERIC_NOP7
675 #define ASM_NOP8 GENERIC_NOP8
678 #define ASM_NOP_MAX 8
680 /* Prefetch instructions for Pentium III and AMD Athlon */
681 /* It's not worth to care about 3dnow! prefetches for the K6
682 because they are microcoded there and very slow.
683 However we don't do prefetches for pre XP Athlons currently
684 That should be fixed. */
685 #define ARCH_HAS_PREFETCH
686 static inline void prefetch(const void *x)
688 alternative_input(ASM_NOP4,
694 #define ARCH_HAS_PREFETCH
695 #define ARCH_HAS_PREFETCHW
696 #define ARCH_HAS_SPINLOCK_PREFETCH
698 /* 3dnow! prefetch to get an exclusive cache line. Useful for
699 spinlocks to avoid one state transition in the cache coherency protocol. */
700 static inline void prefetchw(const void *x)
702 alternative_input(ASM_NOP4,
707 #define spin_lock_prefetch(x) prefetchw(x)
709 extern void select_idle_routine(const struct cpuinfo_x86 *c);
711 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
713 extern unsigned long boot_option_idle_override;
714 extern void enable_sep_cpu(void);
715 extern int sysenter_setup(void);
718 extern void mtrr_ap_init(void);
719 extern void mtrr_bp_init(void);
721 #define mtrr_ap_init() do {} while (0)
722 #define mtrr_bp_init() do {} while (0)
725 #ifdef CONFIG_X86_MCE
726 extern void mcheck_init(struct cpuinfo_x86 *c);
728 #define mcheck_init(c) do {} while(0)
731 #endif /* __ASM_I386_PROCESSOR_H */