2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
31 #define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
63 int x86_cache_alignment; /* In bytes */
69 unsigned long loops_per_jiffy;
71 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
73 unsigned char x86_max_cores; /* cpuid returned max cores value */
75 unsigned short x86_clflush_size;
77 unsigned char booted_cores; /* number of cores as seen by OS */
78 __u8 phys_proc_id; /* Physical processor id. */
79 __u8 cpu_core_id; /* Core id */
81 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
83 #define X86_VENDOR_INTEL 0
84 #define X86_VENDOR_CYRIX 1
85 #define X86_VENDOR_AMD 2
86 #define X86_VENDOR_UMC 3
87 #define X86_VENDOR_NEXGEN 4
88 #define X86_VENDOR_CENTAUR 5
89 #define X86_VENDOR_RISE 6
90 #define X86_VENDOR_TRANSMETA 7
91 #define X86_VENDOR_NSC 8
92 #define X86_VENDOR_NUM 9
93 #define X86_VENDOR_UNKNOWN 0xff
96 * capabilities of CPUs
99 extern struct cpuinfo_x86 boot_cpu_data;
100 extern struct cpuinfo_x86 new_cpu_data;
101 extern struct tss_struct doublefault_tss;
102 DECLARE_PER_CPU(struct tss_struct, init_tss);
105 extern struct cpuinfo_x86 cpu_data[];
106 #define current_cpu_data cpu_data[smp_processor_id()]
108 #define cpu_data (&boot_cpu_data)
109 #define current_cpu_data boot_cpu_data
112 extern int cpu_llc_id[NR_CPUS];
113 extern char ignore_fpu_irq;
115 extern void identify_cpu(struct cpuinfo_x86 *);
116 extern void print_cpu_info(struct cpuinfo_x86 *);
117 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
118 extern unsigned short num_cache_leaves;
121 extern void detect_ht(struct cpuinfo_x86 *c);
123 static inline void detect_ht(struct cpuinfo_x86 *c) {}
129 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
130 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
131 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
132 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
133 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
134 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
135 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
136 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
137 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
138 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
139 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
140 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
141 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
142 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
143 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
144 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
145 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
147 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
148 unsigned int *ecx, unsigned int *edx)
150 /* ecx is often an input as well as an output. */
156 : "0" (*eax), "2" (*ecx));
160 * Generic CPUID function
161 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
162 * resulting in stale register contents being returned.
164 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
168 __cpuid(eax, ebx, ecx, edx);
171 /* Some CPUID calls want 'count' to be placed in ecx */
172 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
177 __cpuid(eax, ebx, ecx, edx);
181 * CPUID functions returning a single datum
183 static inline unsigned int cpuid_eax(unsigned int op)
185 unsigned int eax, ebx, ecx, edx;
187 cpuid(op, &eax, &ebx, &ecx, &edx);
190 static inline unsigned int cpuid_ebx(unsigned int op)
192 unsigned int eax, ebx, ecx, edx;
194 cpuid(op, &eax, &ebx, &ecx, &edx);
197 static inline unsigned int cpuid_ecx(unsigned int op)
199 unsigned int eax, ebx, ecx, edx;
201 cpuid(op, &eax, &ebx, &ecx, &edx);
204 static inline unsigned int cpuid_edx(unsigned int op)
206 unsigned int eax, ebx, ecx, edx;
208 cpuid(op, &eax, &ebx, &ecx, &edx);
212 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
215 * Intel CPU features in CR4
217 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
218 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
219 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
220 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
221 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
222 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
223 #define X86_CR4_MCE 0x0040 /* Machine check enable */
224 #define X86_CR4_PGE 0x0080 /* enable global pages */
225 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
226 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
227 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
230 * Save the cr4 feature set we're using (ie
231 * Pentium 4MB enable and PPro Global page
232 * enable), so that any CPU's that boot up
233 * after us can get the correct flags.
235 extern unsigned long mmu_cr4_features;
237 static inline void set_in_cr4 (unsigned long mask)
240 mmu_cr4_features |= mask;
246 static inline void clear_in_cr4 (unsigned long mask)
249 mmu_cr4_features &= ~mask;
256 * NSC/Cyrix CPU configuration register indexes
259 #define CX86_PCR0 0x20
260 #define CX86_GCR 0xb8
261 #define CX86_CCR0 0xc0
262 #define CX86_CCR1 0xc1
263 #define CX86_CCR2 0xc2
264 #define CX86_CCR3 0xc3
265 #define CX86_CCR4 0xe8
266 #define CX86_CCR5 0xe9
267 #define CX86_CCR6 0xea
268 #define CX86_CCR7 0xeb
269 #define CX86_PCR1 0xf0
270 #define CX86_DIR0 0xfe
271 #define CX86_DIR1 0xff
272 #define CX86_ARR_BASE 0xc4
273 #define CX86_RCR_BASE 0xdc
276 * NSC/Cyrix CPU indexed register access macros
279 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
281 #define setCx86(reg, data) do { \
283 outb((data), 0x23); \
286 /* Stop speculative execution */
287 static inline void sync_core(void)
290 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
293 static inline void __monitor(const void *eax, unsigned long ecx,
296 /* "monitor %eax,%ecx,%edx;" */
298 ".byte 0x0f,0x01,0xc8;"
299 : :"a" (eax), "c" (ecx), "d"(edx));
302 static inline void __mwait(unsigned long eax, unsigned long ecx)
304 /* "mwait %eax,%ecx;" */
306 ".byte 0x0f,0x01,0xc9;"
307 : :"a" (eax), "c" (ecx));
310 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
312 /* from system description table in BIOS. Mostly for MCA use, but
313 others may find it useful. */
314 extern unsigned int machine_id;
315 extern unsigned int machine_submodel_id;
316 extern unsigned int BIOS_revision;
317 extern unsigned int mca_pentium_flag;
319 /* Boot loader type from the setup header */
320 extern int bootloader_type;
323 * User space process size: 3GB (default).
325 #define TASK_SIZE (PAGE_OFFSET)
327 /* This decides where the kernel will search for a free chunk of vm
328 * space during mmap's.
330 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
332 #define HAVE_ARCH_PICK_MMAP_LAYOUT
337 #define IO_BITMAP_BITS 65536
338 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
339 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
340 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
341 #define INVALID_IO_BITMAP_OFFSET 0x8000
342 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
344 struct i387_fsave_struct {
352 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
353 long status; /* software status information */
356 struct i387_fxsave_struct {
367 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
368 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
370 } __attribute__ ((aligned (16)));
372 struct i387_soft_struct {
380 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
381 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
383 unsigned long entry_eip;
387 struct i387_fsave_struct fsave;
388 struct i387_fxsave_struct fxsave;
389 struct i387_soft_struct soft;
396 struct thread_struct;
399 unsigned short back_link,__blh;
401 unsigned short ss0,__ss0h;
403 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
405 unsigned short ss2,__ss2h;
408 unsigned long eflags;
409 unsigned long eax,ecx,edx,ebx;
414 unsigned short es, __esh;
415 unsigned short cs, __csh;
416 unsigned short ss, __ssh;
417 unsigned short ds, __dsh;
418 unsigned short fs, __fsh;
419 unsigned short gs, __gsh;
420 unsigned short ldt, __ldth;
421 unsigned short trace, io_bitmap_base;
423 * The extra 1 is there because the CPU will access an
424 * additional byte beyond the end of the IO permission
425 * bitmap. The extra byte must be all 1 bits, and must
426 * be within the limit.
428 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
430 * Cache the current maximum and the last task that used the bitmap:
432 unsigned long io_bitmap_max;
433 struct thread_struct *io_bitmap_owner;
435 * pads the TSS to be cacheline-aligned (size is 0x100)
437 unsigned long __cacheline_filler[35];
439 * .. and then another 0x100 bytes for emergency kernel stack
441 unsigned long stack[64];
442 } __attribute__((packed));
444 #define ARCH_MIN_TASKALIGN 16
446 struct thread_struct {
447 /* cached TLS descriptors. */
448 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
450 unsigned long sysenter_cs;
455 /* Hardware debugging registers */
456 unsigned long debugreg[8]; /* %%db0-7 debug registers */
458 unsigned long cr2, trap_no, error_code;
459 /* floating point info */
460 union i387_union i387;
461 /* virtual 86 mode info */
462 struct vm86_struct __user * vm86_info;
463 unsigned long screen_bitmap;
464 unsigned long v86flags, v86mask, saved_esp0;
465 unsigned int saved_fs, saved_gs;
467 unsigned long *io_bitmap_ptr;
469 /* max allowed port in the bitmap, in bytes: */
470 unsigned long io_bitmap_max;
473 #define INIT_THREAD { \
475 .sysenter_cs = __KERNEL_CS, \
476 .io_bitmap_ptr = NULL, \
477 .gs = __KERNEL_PDA, \
481 * Note that the .io_bitmap member must be extra-big. This is because
482 * the CPU will access an additional byte beyond the end of the IO
483 * permission bitmap. The extra byte must be all 1 bits, and must
484 * be within the limit.
487 .esp0 = sizeof(init_stack) + (long)&init_stack, \
488 .ss0 = __KERNEL_DS, \
489 .ss1 = __KERNEL_CS, \
490 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
491 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
494 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
496 tss->esp0 = thread->esp0;
497 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
498 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
499 tss->ss1 = thread->sysenter_cs;
500 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
504 #define start_thread(regs, new_eip, new_esp) do { \
505 __asm__("movl %0,%%fs": :"r" (0)); \
508 regs->xds = __USER_DS; \
509 regs->xes = __USER_DS; \
510 regs->xss = __USER_DS; \
511 regs->xcs = __USER_CS; \
512 regs->eip = new_eip; \
513 regs->esp = new_esp; \
517 * These special macros can be used to get or set a debugging register
519 #define get_debugreg(var, register) \
520 __asm__("movl %%db" #register ", %0" \
522 #define set_debugreg(value, register) \
523 __asm__("movl %0,%%db" #register \
528 * Set IOPL bits in EFLAGS from given mask
530 static inline void set_iopl_mask(unsigned mask)
533 __asm__ __volatile__ ("pushfl;"
540 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
543 /* Forward declaration, a strange C thing */
547 /* Free all resources held by a thread. */
548 extern void release_thread(struct task_struct *);
550 /* Prepare to copy thread state - unlazy all lazy status */
551 extern void prepare_to_copy(struct task_struct *tsk);
554 * create a kernel thread without removing it from tasklists
556 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
558 extern unsigned long thread_saved_pc(struct task_struct *tsk);
559 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
561 unsigned long get_wchan(struct task_struct *p);
563 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
564 #define KSTK_TOP(info) \
566 unsigned long *__ptr = (unsigned long *)(info); \
567 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
571 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
572 * This is necessary to guarantee that the entire "struct pt_regs"
573 * is accessable even if the CPU haven't stored the SS/ESP registers
574 * on the stack (interrupt gate does not save these registers
575 * when switching to the same priv ring).
576 * Therefore beware: accessing the xss/esp fields of the
577 * "struct pt_regs" is possible, but they may contain the
578 * completely wrong values.
580 #define task_pt_regs(task) \
582 struct pt_regs *__regs__; \
583 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
587 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
588 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
591 struct microcode_header {
599 unsigned int datasize;
600 unsigned int totalsize;
601 unsigned int reserved[3];
605 struct microcode_header hdr;
606 unsigned int bits[0];
609 typedef struct microcode microcode_t;
610 typedef struct microcode_header microcode_header_t;
612 /* microcode format is extended from prescott processors */
613 struct extended_signature {
619 struct extended_sigtable {
622 unsigned int reserved[3];
623 struct extended_signature sigs[0];
626 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
627 static inline void rep_nop(void)
629 __asm__ __volatile__("rep;nop": : :"memory");
632 #define cpu_relax() rep_nop()
634 /* generic versions from gas */
635 #define GENERIC_NOP1 ".byte 0x90\n"
636 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
637 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
638 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
639 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
640 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
641 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
642 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
645 #define K8_NOP1 GENERIC_NOP1
646 #define K8_NOP2 ".byte 0x66,0x90\n"
647 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
648 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
649 #define K8_NOP5 K8_NOP3 K8_NOP2
650 #define K8_NOP6 K8_NOP3 K8_NOP3
651 #define K8_NOP7 K8_NOP4 K8_NOP3
652 #define K8_NOP8 K8_NOP4 K8_NOP4
655 /* uses eax dependencies (arbitary choice) */
656 #define K7_NOP1 GENERIC_NOP1
657 #define K7_NOP2 ".byte 0x8b,0xc0\n"
658 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
659 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
660 #define K7_NOP5 K7_NOP4 ASM_NOP1
661 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
662 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
663 #define K7_NOP8 K7_NOP7 ASM_NOP1
666 #define ASM_NOP1 K8_NOP1
667 #define ASM_NOP2 K8_NOP2
668 #define ASM_NOP3 K8_NOP3
669 #define ASM_NOP4 K8_NOP4
670 #define ASM_NOP5 K8_NOP5
671 #define ASM_NOP6 K8_NOP6
672 #define ASM_NOP7 K8_NOP7
673 #define ASM_NOP8 K8_NOP8
674 #elif defined(CONFIG_MK7)
675 #define ASM_NOP1 K7_NOP1
676 #define ASM_NOP2 K7_NOP2
677 #define ASM_NOP3 K7_NOP3
678 #define ASM_NOP4 K7_NOP4
679 #define ASM_NOP5 K7_NOP5
680 #define ASM_NOP6 K7_NOP6
681 #define ASM_NOP7 K7_NOP7
682 #define ASM_NOP8 K7_NOP8
684 #define ASM_NOP1 GENERIC_NOP1
685 #define ASM_NOP2 GENERIC_NOP2
686 #define ASM_NOP3 GENERIC_NOP3
687 #define ASM_NOP4 GENERIC_NOP4
688 #define ASM_NOP5 GENERIC_NOP5
689 #define ASM_NOP6 GENERIC_NOP6
690 #define ASM_NOP7 GENERIC_NOP7
691 #define ASM_NOP8 GENERIC_NOP8
694 #define ASM_NOP_MAX 8
696 /* Prefetch instructions for Pentium III and AMD Athlon */
697 /* It's not worth to care about 3dnow! prefetches for the K6
698 because they are microcoded there and very slow.
699 However we don't do prefetches for pre XP Athlons currently
700 That should be fixed. */
701 #define ARCH_HAS_PREFETCH
702 static inline void prefetch(const void *x)
704 alternative_input(ASM_NOP4,
710 #define ARCH_HAS_PREFETCH
711 #define ARCH_HAS_PREFETCHW
712 #define ARCH_HAS_SPINLOCK_PREFETCH
714 /* 3dnow! prefetch to get an exclusive cache line. Useful for
715 spinlocks to avoid one state transition in the cache coherency protocol. */
716 static inline void prefetchw(const void *x)
718 alternative_input(ASM_NOP4,
723 #define spin_lock_prefetch(x) prefetchw(x)
725 extern void select_idle_routine(const struct cpuinfo_x86 *c);
727 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
729 extern unsigned long boot_option_idle_override;
730 extern void enable_sep_cpu(void);
731 extern int sysenter_setup(void);
733 extern int init_gdt(int cpu, struct task_struct *idle);
734 extern void secondary_cpu_init(void);
736 #endif /* __ASM_I386_PROCESSOR_H */