2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
23 #include <linux/init.h>
24 #include <asm/processor-flags.h>
26 /* flag for disabling the tsc */
27 extern int tsc_disable;
33 #define desc_empty(desc) \
34 (!((desc)->a | (desc)->b))
36 #define desc_equal(desc1, desc2) \
37 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
39 * Default implementation of macro that returns current
40 * instruction pointer ("program counter").
42 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
45 * CPU type and hardware bug flags. Kept separately for each CPU.
46 * Members of this structure are referenced in head.S, so think twice
47 * before touching them. [mj]
51 __u8 x86; /* CPU family */
52 __u8 x86_vendor; /* CPU vendor */
55 char wp_works_ok; /* It doesn't on 386's */
56 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
59 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
60 unsigned long x86_capability[NCAPINTS];
61 char x86_vendor_id[16];
62 char x86_model_id[64];
63 int x86_cache_size; /* in KB - valid for CPUS which support this
65 int x86_cache_alignment; /* In bytes */
71 unsigned long loops_per_jiffy;
73 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
75 unsigned char x86_max_cores; /* cpuid returned max cores value */
77 unsigned short x86_clflush_size;
79 unsigned char booted_cores; /* number of cores as seen by OS */
80 __u8 phys_proc_id; /* Physical processor id. */
81 __u8 cpu_core_id; /* Core id */
83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
85 #define X86_VENDOR_INTEL 0
86 #define X86_VENDOR_CYRIX 1
87 #define X86_VENDOR_AMD 2
88 #define X86_VENDOR_UMC 3
89 #define X86_VENDOR_NEXGEN 4
90 #define X86_VENDOR_CENTAUR 5
91 #define X86_VENDOR_TRANSMETA 7
92 #define X86_VENDOR_NSC 8
93 #define X86_VENDOR_NUM 9
94 #define X86_VENDOR_UNKNOWN 0xff
97 * capabilities of CPUs
100 extern struct cpuinfo_x86 boot_cpu_data;
101 extern struct cpuinfo_x86 new_cpu_data;
102 extern struct tss_struct doublefault_tss;
103 DECLARE_PER_CPU(struct tss_struct, init_tss);
106 extern struct cpuinfo_x86 cpu_data[];
107 #define current_cpu_data cpu_data[smp_processor_id()]
109 #define cpu_data (&boot_cpu_data)
110 #define current_cpu_data boot_cpu_data
113 extern int cpu_llc_id[NR_CPUS];
114 extern char ignore_fpu_irq;
116 void __init cpu_detect(struct cpuinfo_x86 *c);
118 extern void identify_boot_cpu(void);
119 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
120 extern void print_cpu_info(struct cpuinfo_x86 *);
121 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
122 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
123 extern unsigned short num_cache_leaves;
126 extern void detect_ht(struct cpuinfo_x86 *c);
128 static inline void detect_ht(struct cpuinfo_x86 *c) {}
131 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
132 unsigned int *ecx, unsigned int *edx)
134 /* ecx is often an input as well as an output. */
140 : "0" (*eax), "2" (*ecx));
143 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
146 * Save the cr4 feature set we're using (ie
147 * Pentium 4MB enable and PPro Global page
148 * enable), so that any CPU's that boot up
149 * after us can get the correct flags.
151 extern unsigned long mmu_cr4_features;
153 static inline void set_in_cr4 (unsigned long mask)
156 mmu_cr4_features |= mask;
162 static inline void clear_in_cr4 (unsigned long mask)
165 mmu_cr4_features &= ~mask;
172 * NSC/Cyrix CPU indexed register access macros
175 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
177 #define setCx86(reg, data) do { \
179 outb((data), 0x23); \
182 /* Stop speculative execution */
183 static inline void sync_core(void)
186 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
189 static inline void __monitor(const void *eax, unsigned long ecx,
192 /* "monitor %eax,%ecx,%edx;" */
194 ".byte 0x0f,0x01,0xc8;"
195 : :"a" (eax), "c" (ecx), "d"(edx));
198 static inline void __mwait(unsigned long eax, unsigned long ecx)
200 /* "mwait %eax,%ecx;" */
202 ".byte 0x0f,0x01,0xc9;"
203 : :"a" (eax), "c" (ecx));
206 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
208 /* from system description table in BIOS. Mostly for MCA use, but
209 others may find it useful. */
210 extern unsigned int machine_id;
211 extern unsigned int machine_submodel_id;
212 extern unsigned int BIOS_revision;
213 extern unsigned int mca_pentium_flag;
215 /* Boot loader type from the setup header */
216 extern int bootloader_type;
219 * User space process size: 3GB (default).
221 #define TASK_SIZE (PAGE_OFFSET)
223 /* This decides where the kernel will search for a free chunk of vm
224 * space during mmap's.
226 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
228 #define HAVE_ARCH_PICK_MMAP_LAYOUT
230 extern void hard_disable_TSC(void);
231 extern void disable_TSC(void);
232 extern void hard_enable_TSC(void);
237 #define IO_BITMAP_BITS 65536
238 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
239 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
240 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
241 #define INVALID_IO_BITMAP_OFFSET 0x8000
242 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
244 struct i387_fsave_struct {
252 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
253 long status; /* software status information */
256 struct i387_fxsave_struct {
267 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
268 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
270 } __attribute__ ((aligned (16)));
272 struct i387_soft_struct {
280 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
281 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
283 unsigned long entry_eip;
287 struct i387_fsave_struct fsave;
288 struct i387_fxsave_struct fxsave;
289 struct i387_soft_struct soft;
296 struct thread_struct;
298 /* This is the TSS defined by the hardware. */
300 unsigned short back_link,__blh;
302 unsigned short ss0,__ss0h;
304 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
306 unsigned short ss2,__ss2h;
309 unsigned long eflags;
310 unsigned long eax,ecx,edx,ebx;
315 unsigned short es, __esh;
316 unsigned short cs, __csh;
317 unsigned short ss, __ssh;
318 unsigned short ds, __dsh;
319 unsigned short fs, __fsh;
320 unsigned short gs, __gsh;
321 unsigned short ldt, __ldth;
322 unsigned short trace, io_bitmap_base;
323 } __attribute__((packed));
326 struct i386_hw_tss x86_tss;
329 * The extra 1 is there because the CPU will access an
330 * additional byte beyond the end of the IO permission
331 * bitmap. The extra byte must be all 1 bits, and must
332 * be within the limit.
334 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
336 * Cache the current maximum and the last task that used the bitmap:
338 unsigned long io_bitmap_max;
339 struct thread_struct *io_bitmap_owner;
341 * pads the TSS to be cacheline-aligned (size is 0x100)
343 unsigned long __cacheline_filler[35];
345 * .. and then another 0x100 bytes for emergency kernel stack
347 unsigned long stack[64];
348 } __attribute__((packed));
350 #define ARCH_MIN_TASKALIGN 16
352 struct thread_struct {
353 /* cached TLS descriptors. */
354 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
356 unsigned long sysenter_cs;
361 /* Hardware debugging registers */
362 unsigned long debugreg[8]; /* %%db0-7 debug registers */
364 unsigned long cr2, trap_no, error_code;
365 /* floating point info */
366 union i387_union i387;
367 /* virtual 86 mode info */
368 struct vm86_struct __user * vm86_info;
369 unsigned long screen_bitmap;
370 unsigned long v86flags, v86mask, saved_esp0;
371 unsigned int saved_fs, saved_gs;
373 unsigned long *io_bitmap_ptr;
375 /* max allowed port in the bitmap, in bytes: */
376 unsigned long io_bitmap_max;
379 #define INIT_THREAD { \
380 .esp0 = sizeof(init_stack) + (long)&init_stack, \
382 .sysenter_cs = __KERNEL_CS, \
383 .io_bitmap_ptr = NULL, \
384 .fs = __KERNEL_PERCPU, \
388 * Note that the .io_bitmap member must be extra-big. This is because
389 * the CPU will access an additional byte beyond the end of the IO
390 * permission bitmap. The extra byte must be all 1 bits, and must
391 * be within the limit.
395 .esp0 = sizeof(init_stack) + (long)&init_stack, \
396 .ss0 = __KERNEL_DS, \
397 .ss1 = __KERNEL_CS, \
398 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
400 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
403 #define start_thread(regs, new_eip, new_esp) do { \
404 __asm__("movl %0,%%gs": :"r" (0)); \
407 regs->xds = __USER_DS; \
408 regs->xes = __USER_DS; \
409 regs->xss = __USER_DS; \
410 regs->xcs = __USER_CS; \
411 regs->eip = new_eip; \
412 regs->esp = new_esp; \
415 /* Forward declaration, a strange C thing */
419 /* Free all resources held by a thread. */
420 extern void release_thread(struct task_struct *);
422 /* Prepare to copy thread state - unlazy all lazy status */
423 extern void prepare_to_copy(struct task_struct *tsk);
426 * create a kernel thread without removing it from tasklists
428 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
430 extern unsigned long thread_saved_pc(struct task_struct *tsk);
431 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
433 unsigned long get_wchan(struct task_struct *p);
435 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
436 #define KSTK_TOP(info) \
438 unsigned long *__ptr = (unsigned long *)(info); \
439 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
443 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
444 * This is necessary to guarantee that the entire "struct pt_regs"
445 * is accessable even if the CPU haven't stored the SS/ESP registers
446 * on the stack (interrupt gate does not save these registers
447 * when switching to the same priv ring).
448 * Therefore beware: accessing the xss/esp fields of the
449 * "struct pt_regs" is possible, but they may contain the
450 * completely wrong values.
452 #define task_pt_regs(task) \
454 struct pt_regs *__regs__; \
455 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
459 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
460 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
463 struct microcode_header {
471 unsigned int datasize;
472 unsigned int totalsize;
473 unsigned int reserved[3];
477 struct microcode_header hdr;
478 unsigned int bits[0];
481 typedef struct microcode microcode_t;
482 typedef struct microcode_header microcode_header_t;
484 /* microcode format is extended from prescott processors */
485 struct extended_signature {
491 struct extended_sigtable {
494 unsigned int reserved[3];
495 struct extended_signature sigs[0];
498 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
499 static inline void rep_nop(void)
501 __asm__ __volatile__("rep;nop": : :"memory");
504 #define cpu_relax() rep_nop()
506 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
508 tss->x86_tss.esp0 = thread->esp0;
509 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
510 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
511 tss->x86_tss.ss1 = thread->sysenter_cs;
512 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
517 static inline unsigned long native_get_debugreg(int regno)
519 unsigned long val = 0; /* Damn you, gcc! */
523 asm("movl %%db0, %0" :"=r" (val)); break;
525 asm("movl %%db1, %0" :"=r" (val)); break;
527 asm("movl %%db2, %0" :"=r" (val)); break;
529 asm("movl %%db3, %0" :"=r" (val)); break;
531 asm("movl %%db6, %0" :"=r" (val)); break;
533 asm("movl %%db7, %0" :"=r" (val)); break;
540 static inline void native_set_debugreg(int regno, unsigned long value)
544 asm("movl %0,%%db0" : /* no output */ :"r" (value));
547 asm("movl %0,%%db1" : /* no output */ :"r" (value));
550 asm("movl %0,%%db2" : /* no output */ :"r" (value));
553 asm("movl %0,%%db3" : /* no output */ :"r" (value));
556 asm("movl %0,%%db6" : /* no output */ :"r" (value));
559 asm("movl %0,%%db7" : /* no output */ :"r" (value));
567 * Set IOPL bits in EFLAGS from given mask
569 static inline void native_set_iopl_mask(unsigned mask)
572 __asm__ __volatile__ ("pushfl;"
579 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
582 #ifdef CONFIG_PARAVIRT
583 #include <asm/paravirt.h>
585 #define paravirt_enabled() 0
586 #define __cpuid native_cpuid
588 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
590 native_load_esp0(tss, thread);
594 * These special macros can be used to get or set a debugging register
596 #define get_debugreg(var, register) \
597 (var) = native_get_debugreg(register)
598 #define set_debugreg(value, register) \
599 native_set_debugreg(register, value)
601 #define set_iopl_mask native_set_iopl_mask
602 #endif /* CONFIG_PARAVIRT */
605 * Generic CPUID function
606 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
607 * resulting in stale register contents being returned.
609 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
613 __cpuid(eax, ebx, ecx, edx);
616 /* Some CPUID calls want 'count' to be placed in ecx */
617 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
622 __cpuid(eax, ebx, ecx, edx);
626 * CPUID functions returning a single datum
628 static inline unsigned int cpuid_eax(unsigned int op)
630 unsigned int eax, ebx, ecx, edx;
632 cpuid(op, &eax, &ebx, &ecx, &edx);
635 static inline unsigned int cpuid_ebx(unsigned int op)
637 unsigned int eax, ebx, ecx, edx;
639 cpuid(op, &eax, &ebx, &ecx, &edx);
642 static inline unsigned int cpuid_ecx(unsigned int op)
644 unsigned int eax, ebx, ecx, edx;
646 cpuid(op, &eax, &ebx, &ecx, &edx);
649 static inline unsigned int cpuid_edx(unsigned int op)
651 unsigned int eax, ebx, ecx, edx;
653 cpuid(op, &eax, &ebx, &ecx, &edx);
657 /* generic versions from gas */
658 #define GENERIC_NOP1 ".byte 0x90\n"
659 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
660 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
661 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
662 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
663 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
664 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
665 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
668 #define K8_NOP1 GENERIC_NOP1
669 #define K8_NOP2 ".byte 0x66,0x90\n"
670 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
671 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
672 #define K8_NOP5 K8_NOP3 K8_NOP2
673 #define K8_NOP6 K8_NOP3 K8_NOP3
674 #define K8_NOP7 K8_NOP4 K8_NOP3
675 #define K8_NOP8 K8_NOP4 K8_NOP4
678 /* uses eax dependencies (arbitary choice) */
679 #define K7_NOP1 GENERIC_NOP1
680 #define K7_NOP2 ".byte 0x8b,0xc0\n"
681 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
682 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
683 #define K7_NOP5 K7_NOP4 ASM_NOP1
684 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
685 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
686 #define K7_NOP8 K7_NOP7 ASM_NOP1
689 #define ASM_NOP1 K8_NOP1
690 #define ASM_NOP2 K8_NOP2
691 #define ASM_NOP3 K8_NOP3
692 #define ASM_NOP4 K8_NOP4
693 #define ASM_NOP5 K8_NOP5
694 #define ASM_NOP6 K8_NOP6
695 #define ASM_NOP7 K8_NOP7
696 #define ASM_NOP8 K8_NOP8
697 #elif defined(CONFIG_MK7)
698 #define ASM_NOP1 K7_NOP1
699 #define ASM_NOP2 K7_NOP2
700 #define ASM_NOP3 K7_NOP3
701 #define ASM_NOP4 K7_NOP4
702 #define ASM_NOP5 K7_NOP5
703 #define ASM_NOP6 K7_NOP6
704 #define ASM_NOP7 K7_NOP7
705 #define ASM_NOP8 K7_NOP8
707 #define ASM_NOP1 GENERIC_NOP1
708 #define ASM_NOP2 GENERIC_NOP2
709 #define ASM_NOP3 GENERIC_NOP3
710 #define ASM_NOP4 GENERIC_NOP4
711 #define ASM_NOP5 GENERIC_NOP5
712 #define ASM_NOP6 GENERIC_NOP6
713 #define ASM_NOP7 GENERIC_NOP7
714 #define ASM_NOP8 GENERIC_NOP8
717 #define ASM_NOP_MAX 8
719 /* Prefetch instructions for Pentium III and AMD Athlon */
720 /* It's not worth to care about 3dnow! prefetches for the K6
721 because they are microcoded there and very slow.
722 However we don't do prefetches for pre XP Athlons currently
723 That should be fixed. */
724 #define ARCH_HAS_PREFETCH
725 static inline void prefetch(const void *x)
727 alternative_input(ASM_NOP4,
733 #define ARCH_HAS_PREFETCH
734 #define ARCH_HAS_PREFETCHW
735 #define ARCH_HAS_SPINLOCK_PREFETCH
737 /* 3dnow! prefetch to get an exclusive cache line. Useful for
738 spinlocks to avoid one state transition in the cache coherency protocol. */
739 static inline void prefetchw(const void *x)
741 alternative_input(ASM_NOP4,
746 #define spin_lock_prefetch(x) prefetchw(x)
748 extern void select_idle_routine(const struct cpuinfo_x86 *c);
750 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
752 extern unsigned long boot_option_idle_override;
753 extern void enable_sep_cpu(void);
754 extern int sysenter_setup(void);
756 /* Defined in head.S */
757 extern struct Xgt_desc_struct early_gdt_descr;
759 extern void cpu_set_gdt(int);
760 extern void switch_to_new_gdt(void);
761 extern void cpu_init(void);
762 extern void init_gdt(int cpu);
764 extern int force_mwait;
766 #endif /* __ASM_I386_PROCESSOR_H */