2 * File: include/asm-blackfin/mach-bf548/bf548.h
7 * Description: System MMR register and memory map for ADSP-BF548
10 * Copyright 2004-2007 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #ifndef __MACH_BF548_H__
31 #define __MACH_BF548_H__
33 /* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
35 #define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
36 #define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */
37 #define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
38 #define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */
39 #define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */
40 #define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | \
41 RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
43 #define OFFSET_(x) ((x) & 0x0000FFFF)
46 #define IMASK_IVG15 0x8000
47 #define IMASK_IVG14 0x4000
48 #define IMASK_IVG13 0x2000
49 #define IMASK_IVG12 0x1000
51 #define IMASK_IVG11 0x0800
52 #define IMASK_IVG10 0x0400
53 #define IMASK_IVG9 0x0200
54 #define IMASK_IVG8 0x0100
56 #define IMASK_IVG7 0x0080
57 #define IMASK_IVGTMR 0x0040
58 #define IMASK_IVGHW 0x0020
60 /***************************/
63 #define BLKFIN_DSUBBANKS 4
64 #define BLKFIN_DWAYS 2
65 #define BLKFIN_DLINES 64
66 #define BLKFIN_ISUBBANKS 4
67 #define BLKFIN_IWAYS 4
68 #define BLKFIN_ILINES 32
88 #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
90 /********************************* EBIU Settings ************************************/
91 #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
92 #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
94 #ifdef CONFIG_C_AMBEN_ALL
95 #define V_AMBEN AMBEN_ALL
100 #ifdef CONFIG_C_AMBEN_B0
101 #define V_AMBEN AMBEN_B0
103 #ifdef CONFIG_C_AMBEN_B0_B1
104 #define V_AMBEN AMBEN_B0_B1
106 #ifdef CONFIG_C_AMBEN_B0_B1_B2
107 #define V_AMBEN AMBEN_B0_B1_B2
109 #ifdef CONFIG_C_AMCKEN
110 #define V_AMCKEN AMCKEN
114 #ifdef CONFIG_C_CDPRIO
115 #define V_CDPRIO 0x100
120 #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
122 #define MAX_VC 650000000
123 #define MIN_VC 50000000
125 /********************************PLL Settings **************************************/
126 #ifdef CONFIG_BFIN_KERNEL_CLOCK
127 #if (CONFIG_VCO_MULT < 0)
128 #error "VCO Multiplier is less than 0. Please select a different value"
131 #if (CONFIG_VCO_MULT == 0)
132 #error "VCO Multiplier should be greater than 0. Please select a different value"
135 #if (CONFIG_VCO_MULT > 64)
136 #error "VCO Multiplier is more than 64. Please select a different value"
139 #ifndef CONFIG_CLKIN_HALF
140 #define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
142 #define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
145 #ifndef CONFIG_PLL_BYPASS
146 #define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
147 #define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
149 #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
150 #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
153 #if (CONFIG_SCLK_DIV < 1)
154 #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
157 #if (CONFIG_SCLK_DIV > 15)
158 #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
161 #if (CONFIG_CCLK_DIV != 1)
162 #if (CONFIG_CCLK_DIV != 2)
163 #if (CONFIG_CCLK_DIV != 4)
164 #if (CONFIG_CCLK_DIV != 8)
165 #error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
171 #if (CONFIG_VCO_HZ > MAX_VC)
172 #error "VCO selected is more than maximum value. Please change the VCO multipler"
175 #if (CONFIG_SCLK_HZ > 133000000)
176 #error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
179 #if (CONFIG_SCLK_HZ < 27000000)
180 #error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
183 #if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
184 #if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
185 #if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
186 #error "Please select sclk less than cclk"
191 #if (CONFIG_CCLK_DIV == 1)
192 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
194 #if (CONFIG_CCLK_DIV == 2)
195 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
197 #if (CONFIG_CCLK_DIV == 4)
198 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
200 #if (CONFIG_CCLK_DIV == 8)
201 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
203 #ifndef CONFIG_CCLK_ACT_DIV
204 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
207 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
211 #define CPUID 0x027c8000
215 #define CPUID 0x027c8000
219 #define CPUID 0x027c6000
225 #define CPU "UNKNOWN"
229 #if (CONFIG_MEM_SIZE % 4)
230 #error "SDRAM mem size must be multible of 4MB"
233 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
234 #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
235 #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
236 #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
238 /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
240 #define ANOMALY_05000158_WORKAROUND 0x200
241 #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
242 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
243 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
244 #else /*Write Through */
245 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
246 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
250 #define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
251 #define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
252 #define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
253 #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
255 #define SIZE_1K 0x00000400 /* 1K */
256 #define SIZE_4K 0x00001000 /* 4K */
257 #define SIZE_1M 0x00100000 /* 1M */
258 #define SIZE_4M 0x00400000 /* 4M */
260 #define MAX_CPLBS (16 * 2)
263 * Number of required data CPLB switchtable entries
264 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
265 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
266 * 1 for L1 Data Memory
267 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
272 #define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
275 * Number of required instruction CPLB switchtable entries
276 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
277 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
278 * 1 for L1 Instruction Memory
279 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
282 #define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
284 #endif /* __MACH_BF48_H__ */