2 * File: include/asm-blackfin/mach-bf533/anomaly.h
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 /* This file shoule be up to date with:
32 * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
33 * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
34 * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
37 #ifndef _MACH_ANOMALY_H_
38 #define _MACH_ANOMALY_H_
40 /* We do not support 0.1 or 0.2 silicon - sorry */
41 #if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
42 #error Kernel will not work on BF533 Version 0.1 or 0.2
45 /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
46 #if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
47 || defined(CONFIG_BF_REV_0_3))
48 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
49 slot1 and store of a P register in slot 2 is not
51 #define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
52 every corresponding match */
53 #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
55 #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
57 #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
59 #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
60 #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
62 #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
64 #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
66 #define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
67 #define ANOMALY_05000272 /* Certain data cache write through modes fail for
69 #define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
70 #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
71 an edge is detected may clear interrupt */
72 #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
73 DMA system instability */
74 #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
76 #define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
78 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
79 killed in a particular stage*/
80 #define ANOMALY_05000311 /* Erroneous flag pin operations under specific
82 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
83 registers are interrupted */
84 #define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */
85 #define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
86 * Next System MMR Access */
87 #define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
88 * and 1.15V Not Allowed for LQFP Packages */
89 #endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
91 /* These issues only occur on 0.3 or 0.4 BF533 */
92 #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
93 #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
94 updated at the same time. */
95 #define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
96 Cache Fill can be corrupted after or during
97 Instruction DMA if certain core stalls exist */
98 #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
99 Purpose TX or RX modes */
100 #define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
101 preceding memory read */
102 #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
103 inactive channels in certain conditions */
104 #define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
106 #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
107 #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
108 #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
110 #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
111 Differences in certain Conditions */
112 #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
113 #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
115 #define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
116 IDLE around a Change of Control causes
117 unpredictable results */
118 #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
119 shadow of a conditional branch */
120 #define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
122 #define ANOMALY_05000253 /* Maximum external clock speed for Timers */
123 #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
124 interrupt not functional */
125 #define ANOMALY_05000257 /* An interrupt or exception during short Hardware
126 loops may cause the instruction fetch unit to
128 #define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
129 the ICPLB Data registers differ */
130 #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
131 #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
132 #define ANOMALY_05000262 /* Stores to data cache may be lost */
133 #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
134 #define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
135 instruction will cause an infinite stall in the
136 second to last instruction in a hardware loop */
137 #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
138 SPORT external receive and transmit clocks. */
139 #define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
140 internal voltage regulator (VDDint) to increase. */
141 #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
142 internal voltage regulator (VDDint) to decrease */
143 #endif /* issues only occur on 0.3 or 0.4 BF533 */
145 /* These issues are only on 0.4 silicon */
146 #if (defined(CONFIG_BF_REV_0_4))
147 #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
148 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
150 #endif /* issues are only on 0.4 silicon */
152 /* These issues are only on 0.3 silicon */
153 #if defined(CONFIG_BF_REV_0_3)
154 #define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
155 External Frame Syncs */
156 #define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
157 Instruction or Data Fetches, or by Fetches at the
158 boundary of reserved memory space */
159 #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
160 when polarity setting is changed */
161 #define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
163 #define ANOMALY_05000199 /* DMA current address shows wrong value during carry
165 #define ANOMALY_05000201 /* Receive frame sync not ignored during active
166 frames in sport MCM */
167 #define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
169 #if defined(CONFIG_BF533)
170 #define ANOMALY_05000204 /* Incorrect data read with write-through cache and
171 allocate cache lines on reads only mode */
172 #endif /* CONFIG_BF533 */
173 #define ANOMALY_05000207 /* Recovery from "brown-out" condition */
174 #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
176 #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
177 Sync Transmit Mode */
178 #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
179 #endif /* only on 0.3 silicon */
181 #if defined(CONFIG_BF_REV_0_2)
182 #define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not
184 #define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
186 #define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
187 * emulation mode and/or exception, NMI, reset
189 #define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
190 * incorrect if data cache or DMA is active */
191 #define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
193 #define ANOMALY_05000125 /* Erroneous exception when enabling cache */
194 #define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
196 #define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
197 #define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
198 * block in the loader file */
199 #define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
201 #define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
202 * of consecutive dual dag events */
203 #define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
204 * flag is configured to be edge sensitive */
205 #define ANOMALY_05000143 /* A read from external memory may return a wrong
206 * value with data cache enabled */
207 #define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
209 #define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
210 * generate a waveform from PPI_CLK */
211 #define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
213 #define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
215 #define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
216 * device, the upper 8-bits of each word must be
218 #define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
219 #define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
220 * outside of valid channels */
221 #define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
222 * certain PPI mode is in use */
223 #define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
224 * the next system MMR access thinking it should be
226 #define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
227 * sync in certain conditions */
228 #define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
229 #define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
230 * write-through cache data writes */
231 #define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
232 #define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
233 #define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
234 #define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
235 * accumulator saturation */
236 #define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
238 #define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
239 #define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
241 #define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
243 #define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
247 #endif /* _MACH_ANOMALY_H_ */