2 * linux/include/asm-arm/pgtable.h
4 * Copyright (C) 1995-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef _ASMARM_PGTABLE_H
11 #define _ASMARM_PGTABLE_H
13 #include <asm-generic/4level-fixup.h>
15 #include <asm/memory.h>
16 #include <asm/proc-fns.h>
17 #include <asm/arch/vmalloc.h>
20 * Hardware-wise, we have a two level page table structure, where the first
21 * level has 4096 entries, and the second level has 256 entries. Each entry
22 * is one 32-bit word. Most of the bits in the second level entry are used
23 * by hardware, and there aren't any "accessed" and "dirty" bits.
25 * Linux on the other hand has a three level page table structure, which can
26 * be wrapped to fit a two level page table structure easily - using the PGD
27 * and PTE only. However, Linux also expects one "PTE" table per page, and
28 * at least a "dirty" bit.
30 * Therefore, we tweak the implementation slightly - we tell Linux that we
31 * have 2048 entries in the first level, each of which is 8 bytes (iow, two
32 * hardware pointers to the second level.) The second level contains two
33 * hardware PTE tables arranged contiguously, followed by Linux versions
34 * which contain the state information Linux needs. We, therefore, end up
35 * with 512 entries in the "PTE" level.
37 * This leads to the page tables having the following layout:
42 * | |-----> +------------+ +0
43 * +- - - - + +4 | h/w pt 0 |
44 * | |-----> +------------+ +1024
45 * +--------+ +8 | h/w pt 1 |
46 * | | +------------+ +2048
47 * +- - - - + | Linux pt 0 |
48 * | | +------------+ +3072
49 * +--------+ | Linux pt 1 |
50 * | | +------------+ +4096
52 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
53 * PTE_xxx for definitions of bits appearing in the "h/w pt".
55 * PMD_xxx definitions refer to bits in the first level page table.
57 * The "dirty" bit is emulated by only granting hardware write permission
58 * iff the page is marked "writable" and "dirty" in the Linux PTE. This
59 * means that a write to a clean page will cause a permission fault, and
60 * the Linux MM layer will mark the page dirty via handle_pte_fault().
61 * For the hardware to notice the permission change, the TLB entry must
62 * be flushed, and ptep_establish() does that for us.
64 * The "accessed" or "young" bit is emulated by a similar method; we only
65 * allow accesses to the page if the "young" bit is set. Accesses to the
66 * page will cause a fault, and handle_pte_fault() will set the young bit
67 * for us as long as the page is marked present in the corresponding Linux
68 * PTE entry. Again, ptep_establish() will ensure that the TLB is up to
71 * However, when the "young" bit is cleared, we deny access to the page
72 * by clearing the hardware PTE. Currently Linux does not flush the TLB
73 * for us in this case, which means the TLB will retain the transation
74 * until either the TLB entry is evicted under pressure, or a context
75 * switch which changes the user space mapping occurs.
77 #define PTRS_PER_PTE 512
78 #define PTRS_PER_PMD 1
79 #define PTRS_PER_PGD 2048
82 * PMD_SHIFT determines the size of the area a second-level page table can map
83 * PGDIR_SHIFT determines what a third-level page table entry can map
86 #define PGDIR_SHIFT 21
88 #define LIBRARY_TEXT_START 0x0c000000
91 extern void __pte_error(const char *file, int line, unsigned long val);
92 extern void __pmd_error(const char *file, int line, unsigned long val);
93 extern void __pgd_error(const char *file, int line, unsigned long val);
95 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
96 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
97 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
98 #endif /* !__ASSEMBLY__ */
100 #define PMD_SIZE (1UL << PMD_SHIFT)
101 #define PMD_MASK (~(PMD_SIZE-1))
102 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
103 #define PGDIR_MASK (~(PGDIR_SIZE-1))
106 * This is the lowest virtual address we can permit any user space
107 * mapping to be mapped at. This is particularly important for
108 * non-high vector CPUs.
110 #define FIRST_USER_ADDRESS PAGE_SIZE
112 #define FIRST_USER_PGD_NR 1
113 #define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
116 * ARMv6 supersection address mask and size definitions.
118 #define SUPERSECTION_SHIFT 24
119 #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
120 #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
123 * Hardware page table definitions.
125 * + Level 1 descriptor (PMD)
128 #define PMD_TYPE_MASK (3 << 0)
129 #define PMD_TYPE_FAULT (0 << 0)
130 #define PMD_TYPE_TABLE (1 << 0)
131 #define PMD_TYPE_SECT (2 << 0)
132 #define PMD_BIT4 (1 << 4)
133 #define PMD_DOMAIN(x) ((x) << 5)
134 #define PMD_PROTECTION (1 << 9) /* v5 */
138 #define PMD_SECT_BUFFERABLE (1 << 2)
139 #define PMD_SECT_CACHEABLE (1 << 3)
140 #define PMD_SECT_AP_WRITE (1 << 10)
141 #define PMD_SECT_AP_READ (1 << 11)
142 #define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
143 #define PMD_SECT_APX (1 << 15) /* v6 */
144 #define PMD_SECT_S (1 << 16) /* v6 */
145 #define PMD_SECT_nG (1 << 17) /* v6 */
146 #define PMD_SECT_SUPER (1 << 18) /* v6 */
148 #define PMD_SECT_UNCACHED (0)
149 #define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
150 #define PMD_SECT_WT (PMD_SECT_CACHEABLE)
151 #define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
152 #define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
153 #define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
156 * - coarse table (not used)
160 * + Level 2 descriptor (PTE)
163 #define PTE_TYPE_MASK (3 << 0)
164 #define PTE_TYPE_FAULT (0 << 0)
165 #define PTE_TYPE_LARGE (1 << 0)
166 #define PTE_TYPE_SMALL (2 << 0)
167 #define PTE_TYPE_EXT (3 << 0) /* v5 */
168 #define PTE_BUFFERABLE (1 << 2)
169 #define PTE_CACHEABLE (1 << 3)
172 * - extended small page/tiny page
174 #define PTE_EXT_AP_MASK (3 << 4)
175 #define PTE_EXT_AP_UNO_SRO (0 << 4)
176 #define PTE_EXT_AP_UNO_SRW (1 << 4)
177 #define PTE_EXT_AP_URO_SRW (2 << 4)
178 #define PTE_EXT_AP_URW_SRW (3 << 4)
179 #define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
184 #define PTE_SMALL_AP_MASK (0xff << 4)
185 #define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
186 #define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
187 #define PTE_SMALL_AP_URO_SRW (0xaa << 4)
188 #define PTE_SMALL_AP_URW_SRW (0xff << 4)
191 * "Linux" PTE definitions.
193 * We keep two sets of PTEs - the hardware and the linux version.
194 * This allows greater flexibility in the way we map the Linux bits
195 * onto the hardware tables, and allows us to have YOUNG and DIRTY
198 * The PTE table pointer refers to the hardware entries; the "Linux"
199 * entries are stored 1024 bytes below.
201 #define L_PTE_PRESENT (1 << 0)
202 #define L_PTE_FILE (1 << 1) /* only when !PRESENT */
203 #define L_PTE_YOUNG (1 << 1)
204 #define L_PTE_BUFFERABLE (1 << 2) /* matches PTE */
205 #define L_PTE_CACHEABLE (1 << 3) /* matches PTE */
206 #define L_PTE_USER (1 << 4)
207 #define L_PTE_WRITE (1 << 5)
208 #define L_PTE_EXEC (1 << 6)
209 #define L_PTE_DIRTY (1 << 7)
213 #include <asm/domain.h>
215 #define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
216 #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
219 * The following macros handle the cache and bufferable bits...
221 #define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE
222 #define _L_PTE_READ L_PTE_USER | L_PTE_EXEC
224 extern pgprot_t pgprot_kernel;
226 #define PAGE_NONE __pgprot(_L_PTE_DEFAULT)
227 #define PAGE_COPY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
228 #define PAGE_SHARED __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE)
229 #define PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
230 #define PAGE_KERNEL pgprot_kernel
232 #endif /* __ASSEMBLY__ */
235 * The table below defines the page protection levels that we insert into our
236 * Linux page table version. These get translated into the best that the
237 * architecture can perform. Note that on most ARM hardware:
238 * 1) We cannot do execute protection
239 * 2) If we could do execute protection, then read is implied
240 * 3) write implies read permissions
242 #define __P000 PAGE_NONE
243 #define __P001 PAGE_READONLY
244 #define __P010 PAGE_COPY
245 #define __P011 PAGE_COPY
246 #define __P100 PAGE_READONLY
247 #define __P101 PAGE_READONLY
248 #define __P110 PAGE_COPY
249 #define __P111 PAGE_COPY
251 #define __S000 PAGE_NONE
252 #define __S001 PAGE_READONLY
253 #define __S010 PAGE_SHARED
254 #define __S011 PAGE_SHARED
255 #define __S100 PAGE_READONLY
256 #define __S101 PAGE_READONLY
257 #define __S110 PAGE_SHARED
258 #define __S111 PAGE_SHARED
262 * ZERO_PAGE is a global shared page that is always zero: used
263 * for zero-mapped memory areas etc..
265 extern struct page *empty_zero_page;
266 #define ZERO_PAGE(vaddr) (empty_zero_page)
268 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
269 #define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
271 #define pte_none(pte) (!pte_val(pte))
272 #define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0))
273 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
274 #define pte_offset_kernel(dir,addr) (pmd_page_kernel(*(dir)) + __pte_index(addr))
275 #define pte_offset_map(dir,addr) (pmd_page_kernel(*(dir)) + __pte_index(addr))
276 #define pte_offset_map_nested(dir,addr) (pmd_page_kernel(*(dir)) + __pte_index(addr))
277 #define pte_unmap(pte) do { } while (0)
278 #define pte_unmap_nested(pte) do { } while (0)
280 #define set_pte(ptep, pte) cpu_set_pte(ptep,pte)
281 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
284 * The following only work if pte_present() is true.
285 * Undefined behaviour if not..
287 #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT)
288 #define pte_read(pte) (pte_val(pte) & L_PTE_USER)
289 #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE)
290 #define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC)
291 #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY)
292 #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG)
295 * The following only works if pte_present() is not true.
297 #define pte_file(pte) (pte_val(pte) & L_PTE_FILE)
298 #define pte_to_pgoff(x) (pte_val(x) >> 2)
299 #define pgoff_to_pte(x) __pte(((x) << 2) | L_PTE_FILE)
301 #define PTE_FILE_MAX_BITS 30
303 #define PTE_BIT_FUNC(fn,op) \
304 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
306 /*PTE_BIT_FUNC(rdprotect, &= ~L_PTE_USER);*/
307 /*PTE_BIT_FUNC(mkread, |= L_PTE_USER);*/
308 PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
309 PTE_BIT_FUNC(mkwrite, |= L_PTE_WRITE);
310 PTE_BIT_FUNC(exprotect, &= ~L_PTE_EXEC);
311 PTE_BIT_FUNC(mkexec, |= L_PTE_EXEC);
312 PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY);
313 PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY);
314 PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG);
315 PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG);
318 * Mark the prot value as uncacheable and unbufferable.
320 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
321 #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~L_PTE_CACHEABLE)
323 #define pmd_none(pmd) (!pmd_val(pmd))
324 #define pmd_present(pmd) (pmd_val(pmd))
325 #define pmd_bad(pmd) (pmd_val(pmd) & 2)
327 #define copy_pmd(pmdpd,pmdps) \
329 pmdpd[0] = pmdps[0]; \
330 pmdpd[1] = pmdps[1]; \
331 flush_pmd_entry(pmdpd); \
334 #define pmd_clear(pmdp) \
336 pmdp[0] = __pmd(0); \
337 pmdp[1] = __pmd(0); \
338 clean_pmd_entry(pmdp); \
341 static inline pte_t *pmd_page_kernel(pmd_t pmd)
345 ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
346 ptr += PTRS_PER_PTE * sizeof(void *);
351 #define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
354 * Permanent address of a page. We never have highmem, so this is trivial.
356 #define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
359 * Conversion functions: convert a page and protection to a page entry,
360 * and a page entry and page directory to the page they refer to.
362 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
365 * The "pgd_xxx()" functions here are trivial for a folded two-level
366 * setup: the pgd is never bad, and a pmd always exists (as it's folded
367 * into the pgd entry)
369 #define pgd_none(pgd) (0)
370 #define pgd_bad(pgd) (0)
371 #define pgd_present(pgd) (1)
372 #define pgd_clear(pgdp) do { } while (0)
373 #define set_pgd(pgd,pgdp) do { } while (0)
375 #define page_pte_prot(page,prot) mk_pte(page, prot)
376 #define page_pte(page) mk_pte(page, __pgprot(0))
378 /* to find an entry in a page-table-directory */
379 #define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
381 #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
383 /* to find an entry in a kernel page-table-directory */
384 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
386 /* Find an entry in the second-level page table.. */
387 #define pmd_offset(dir, addr) ((pmd_t *)(dir))
389 /* Find an entry in the third-level page table.. */
390 #define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
392 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
394 const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER;
395 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
399 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
401 /* Encode and decode a swap entry.
403 * We support up to 32GB of swap on 4k machines
405 #define __swp_type(x) (((x).val >> 2) & 0x7f)
406 #define __swp_offset(x) ((x).val >> 9)
407 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
408 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
409 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
411 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
412 /* FIXME: this is not correct */
413 #define kern_addr_valid(addr) (1)
415 #include <asm-generic/pgtable.h>
418 * We provide our own arch_get_unmapped_area to cope with VIPT caches.
420 #define HAVE_ARCH_UNMAPPED_AREA
423 * remap a physical address `phys' of size `size' with page protection `prot'
424 * into virtual address `from'
426 #define io_remap_page_range(vma,from,phys,size,prot) \
427 remap_pfn_range(vma, from, (phys) >> PAGE_SHIFT, size, prot)
429 #define io_remap_pfn_range(vma,from,pfn,size,prot) \
430 remap_pfn_range(vma, from, pfn, size, prot)
432 #define MK_IOSPACE_PFN(space, pfn) (pfn)
433 #define GET_IOSPACE(pfn) 0
434 #define GET_PFN(pfn) (pfn)
436 #define pgtable_cache_init() do { } while (0)
438 #endif /* !__ASSEMBLY__ */
440 #endif /* _ASMARM_PGTABLE_H */