2 * include/asm-arm/hardware/iop3xx.h
4 * Intel IOP32X and IOP33X register definitions
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
19 * IOP3XX GPIO handling
25 #define IOP3XX_GPIO_LINE(x) (x)
28 extern void gpio_line_config(int line, int direction);
29 extern int gpio_line_get(int line);
30 extern void gpio_line_set(int line, int value);
36 * IOP3XX processor registers
38 #define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
39 #define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
40 #define IOP3XX_PERIPHERAL_SIZE 0x00002000
41 #define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
42 IOP3XX_PERIPHERAL_SIZE - 1)
43 #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
44 IOP3XX_PERIPHERAL_SIZE - 1)
45 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
46 (IOP3XX_PERIPHERAL_PHYS_BASE\
47 - IOP3XX_PERIPHERAL_VIRT_BASE))
48 #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
50 /* Address Translation Unit */
51 #define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
52 #define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
53 #define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
54 #define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
55 #define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
56 #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
57 #define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
58 #define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
59 #define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
60 #define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
61 #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
62 #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
63 #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
64 #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
65 #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
66 #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
67 #define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
68 #define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
69 #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
70 #define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
71 #define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
72 #define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
73 #define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
74 #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
75 #define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
76 #define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
77 #define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
78 #define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
79 #define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
80 #define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
81 #define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
82 #define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
83 #define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
84 #define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
85 #define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
86 #define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
87 #define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
88 #define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
89 #define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
90 #define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
91 #define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
92 #define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
93 #define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
94 #define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
95 #define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
96 #define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
97 #define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
98 #define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
99 #define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
100 #define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
101 #define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
102 #define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
103 #define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
104 #define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
105 #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
106 #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
107 #define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
108 #define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
109 #define IOP3XX_ATUCR_OUT_EN (1 << 1)
111 #define IOP3XX_INIT_ATU_DEFAULT 0
112 #define IOP3XX_INIT_ATU_DISABLE -1
113 #define IOP3XX_INIT_ATU_ENABLE 1
115 #ifdef CONFIG_IOP3XX_ATU
116 #define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
117 IOP3XX_INIT_ATU_ENABLE : init_atu)
119 #define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
120 IOP3XX_INIT_ATU_DISABLE : init_atu)
124 #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
125 #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
126 #define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
127 #define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
128 #define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
129 #define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
130 #define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
131 #define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
132 #define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
133 #define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
134 #define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
135 #define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
136 #define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
137 #define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
138 #define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
139 #define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
140 #define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
141 #define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
142 #define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
143 #define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
144 #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
147 #define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
148 (0x400 + (chan << 6)))
149 #define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
151 /* Peripheral bus interface */
152 #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
153 #define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
154 #define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
155 #define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
156 #define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
157 #define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
158 #define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
159 #define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
160 #define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
161 #define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
162 #define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
163 #define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
164 #define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
165 #define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
166 #define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
167 #define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
168 #define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
170 /* Peripheral performance monitoring unit */
171 #define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
172 #define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
173 #define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
174 #define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
175 /* PERCR0 DOESN'T EXIST - index from 1! */
176 #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
178 /* General Purpose I/O */
179 #define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000)
180 #define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
181 #define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
184 #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
185 #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
186 #define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
187 #define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
188 #define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
189 #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
190 #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
191 #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
192 #define IOP_TMR_EN 0x02
193 #define IOP_TMR_RELOAD 0x04
194 #define IOP_TMR_PRIVILEGED 0x08
195 #define IOP_TMR_RATIO_1_1 0x00
197 /* Application accelerator unit */
198 #define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
199 #define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
201 /* I2C bus interface unit */
202 #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
203 #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
204 #define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
205 #define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
206 #define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
207 #define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
208 #define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
209 #define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
210 #define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
211 #define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
215 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
217 #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
219 #define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
220 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000
221 #define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
222 #define IOP3XX_PCI_LOWER_IO_BA 0x90000000
223 #define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
224 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
225 #define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
226 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
227 #define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) addr -\
228 IOP3XX_PCI_LOWER_IO_PA) +\
229 IOP3XX_PCI_LOWER_IO_VA)
233 void iop3xx_map_io(void);
234 void iop_init_cp6_handler(void);
235 void iop_init_time(unsigned long tickrate);
236 unsigned long iop_gettimeoffset(void);
238 static inline void write_tmr0(u32 val)
240 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
243 static inline void write_tmr1(u32 val)
245 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
248 static inline u32 read_tcr0(void)
251 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
255 static inline u32 read_tcr1(void)
258 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
262 static inline void write_trr0(u32 val)
264 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
267 static inline void write_trr1(u32 val)
269 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
272 static inline void write_tisr(u32 val)
274 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
277 extern struct platform_device iop3xx_dma_0_channel;
278 extern struct platform_device iop3xx_dma_1_channel;
279 extern struct platform_device iop3xx_aau_channel;
280 extern struct platform_device iop3xx_i2c0_device;
281 extern struct platform_device iop3xx_i2c1_device;