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[ARM] 4816/1: RealView: Move the platform-specific definitions into board-eb.h
[linux-2.6] / include / asm-arm / arch-realview / entry-macro.S
1 /*
2  * include/asm-arm/arch-realview/entry-macro.S
3  *
4  * Low-level IRQ helper macros for RealView platforms
5  *
6  * This file is licensed under  the terms of the GNU General Public
7  * License version 2. This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 #include <asm/hardware.h>
11 #include <asm/hardware/gic.h>
12 #include <asm/arch/board-eb.h>
13
14                 .macro  disable_fiq
15                 .endm
16
17                 .macro  get_irqnr_preamble, base, tmp
18 #ifdef CONFIG_REALVIEW_MPCORE
19                 ldr     \base, =IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE)
20 #else
21                 ldr     \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
22 #endif
23                 .endm
24
25                 .macro  arch_ret_to_user, tmp1, tmp2
26                 .endm
27
28                 /*
29                  * The interrupt numbering scheme is defined in the
30                  * interrupt controller spec.  To wit:
31                  *
32                  * Interrupts 0-15 are IPI
33                  * 16-28 are reserved
34                  * 29-31 are local.  We allow 30 to be used for the watchdog.
35                  * 32-1020 are global
36                  * 1021-1022 are reserved
37                  * 1023 is "spurious" (no interrupt)
38                  *
39                  * For now, we ignore all local interrupts so only return an interrupt if it's
40                  * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
41                  *
42                  * A simple read from the controller will tell us the number of the highest
43                  * priority enabled interrupt.  We then just need to check whether it is in the
44                  * valid range for an IRQ (30-1020 inclusive).
45                  */
46
47                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
48
49                 ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
50
51                 ldr     \tmp, =1021
52
53                 bic     \irqnr, \irqstat, #0x1c00
54
55                 cmp     \irqnr, #29
56                 cmpcc   \irqnr, \irqnr
57                 cmpne   \irqnr, \tmp
58                 cmpcs   \irqnr, \irqnr
59
60                 .endm
61
62                 /* We assume that irqstat (the raw value of the IRQ acknowledge
63                  * register) is preserved from the macro above.
64                  * If there is an IPI, we immediately signal end of interrupt on the
65                  * controller, since this requires the original irqstat value which
66                  * we won't easily be able to recreate later.
67                  */
68
69                 .macro test_for_ipi, irqnr, irqstat, base, tmp
70                 bic     \irqnr, \irqstat, #0x1c00
71                 cmp     \irqnr, #16
72                 strcc   \irqstat, [\base, #GIC_CPU_EOI]
73                 cmpcs   \irqnr, \irqnr
74                 .endm
75
76                 /* As above, this assumes that irqstat and base are preserved.. */
77
78                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
79                 bic     \irqnr, \irqstat, #0x1c00
80                 mov     \tmp, #0
81                 cmp     \irqnr, #29
82                 moveq   \tmp, #1
83                 streq   \irqstat, [\base, #GIC_CPU_EOI]
84                 cmp     \tmp, #0
85                 .endm