2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
21 #define PXA_CS0_PHYS 0x00000000
22 #define PXA_CS1_PHYS 0x04000000
23 #define PXA_CS2_PHYS 0x08000000
24 #define PXA_CS3_PHYS 0x0C000000
25 #define PXA_CS4_PHYS 0x10000000
26 #define PXA_CS5_PHYS 0x14000000
30 * Personal Computer Memory Card International Association (PCMCIA) sockets
33 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
34 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
35 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
36 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
37 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
39 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
40 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
41 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
42 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
44 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
45 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
46 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
47 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
49 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
50 (0x20000000 + (Nb)*PCMCIASp)
51 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
52 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
53 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
54 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
55 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
57 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
58 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
59 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
60 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
62 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
63 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
64 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
65 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
73 #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
74 #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
75 #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
76 #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
77 #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
78 #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
79 #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
80 #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
81 #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
82 #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
83 #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
84 #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
85 #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
86 #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
87 #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
88 #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
90 #define DCSR(x) __REG2(0x40000000, (x) << 2)
92 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
93 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
94 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
96 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
97 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
98 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
99 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
100 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
101 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
102 #define DCSR_EORINTR (1 << 9) /* The end of Receive */
104 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
105 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
106 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
107 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
108 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
110 #define DALGN __REG(0x400000a0) /* DMA Alignment Register */
111 #define DINT __REG(0x400000f0) /* DMA Interrupt Register */
113 #define DRCMR(n) (*(((n) < 64) ? \
114 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
115 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
117 #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
118 #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
119 #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
120 #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
121 #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
122 #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
123 #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
124 #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
125 #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
126 #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
127 #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
128 #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
129 #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
130 #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
131 #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
132 #define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
133 #define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
134 #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
135 #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
136 #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
137 #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
138 #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
139 #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
140 #define DRCMR23 __REG(0x4000015c) /* Reserved */
141 #define DRCMR24 __REG(0x40000160) /* Reserved */
142 #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
143 #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
144 #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
145 #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
146 #define DRCMR29 __REG(0x40000174) /* Reserved */
147 #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
148 #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
149 #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
150 #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
151 #define DRCMR34 __REG(0x40000188) /* Reserved */
152 #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
153 #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
154 #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
155 #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
156 #define DRCMR39 __REG(0x4000019C) /* Reserved */
157 #define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
158 #define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
159 #define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
160 #define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
161 #define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
163 #define DRCMRRXSADR DRCMR2
164 #define DRCMRTXSADR DRCMR3
165 #define DRCMRRXBTRBR DRCMR4
166 #define DRCMRTXBTTHR DRCMR5
167 #define DRCMRRXFFRBR DRCMR6
168 #define DRCMRTXFFTHR DRCMR7
169 #define DRCMRRXMCDR DRCMR8
170 #define DRCMRRXMODR DRCMR9
171 #define DRCMRTXMODR DRCMR10
172 #define DRCMRRXPCDR DRCMR11
173 #define DRCMRTXPCDR DRCMR12
174 #define DRCMRRXSSDR DRCMR13
175 #define DRCMRTXSSDR DRCMR14
176 #define DRCMRRXSS2DR DRCMR15
177 #define DRCMRTXSS2DR DRCMR16
178 #define DRCMRRXICDR DRCMR17
179 #define DRCMRTXICDR DRCMR18
180 #define DRCMRRXSTRBR DRCMR19
181 #define DRCMRTXSTTHR DRCMR20
182 #define DRCMRRXMMC DRCMR21
183 #define DRCMRTXMMC DRCMR22
184 #define DRCMRRXSS3DR DRCMR66
185 #define DRCMRTXSS3DR DRCMR67
186 #define DRCMRUDC(x) DRCMR((x) + 24)
188 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
189 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
191 #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
192 #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
193 #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
194 #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
195 #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
196 #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
197 #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
198 #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
199 #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
200 #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
201 #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
202 #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
203 #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
204 #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
205 #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
206 #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
207 #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
208 #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
209 #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
210 #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
211 #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
212 #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
213 #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
214 #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
215 #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
216 #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
217 #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
218 #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
219 #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
220 #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
221 #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
222 #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
223 #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
224 #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
225 #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
226 #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
227 #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
228 #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
229 #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
230 #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
231 #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
232 #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
233 #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
234 #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
235 #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
236 #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
237 #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
238 #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
239 #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
240 #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
241 #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
242 #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
243 #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
244 #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
245 #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
246 #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
247 #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
248 #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
249 #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
250 #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
251 #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
252 #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
253 #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
254 #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
256 #define DDADR(x) __REG2(0x40000200, (x) << 4)
257 #define DSADR(x) __REG2(0x40000204, (x) << 4)
258 #define DTADR(x) __REG2(0x40000208, (x) << 4)
259 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
261 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
262 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
264 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
265 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
266 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
267 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
268 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
269 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
270 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
271 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
272 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
273 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
274 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
275 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
276 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
277 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
284 /* Full Function UART (FFUART) */
286 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
287 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
288 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
289 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
290 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
291 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
292 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
293 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
294 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
295 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
296 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
297 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
298 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
300 /* Bluetooth UART (BTUART) */
302 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
303 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
304 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
305 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
306 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
307 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
308 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
309 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
310 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
311 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
312 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
313 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
314 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
316 /* Standard UART (STUART) */
318 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
319 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
320 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
321 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
322 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
323 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
324 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
325 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
326 #define STMSR __REG(0x40700018) /* Reserved */
327 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
328 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
329 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
330 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
332 /* Hardware UART (HWUART) */
334 #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
335 #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
336 #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
337 #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
338 #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
339 #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
340 #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
341 #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
342 #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
343 #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
344 #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
345 #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
346 #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
347 #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
348 #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
349 #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
351 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
352 #define IER_UUE (1 << 6) /* UART Unit Enable */
353 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
354 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
355 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
356 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
357 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
358 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
360 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
361 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
362 #define IIR_TOD (1 << 3) /* Time Out Detected */
363 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
364 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
365 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
367 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
368 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
369 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
370 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
371 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
372 #define FCR_ITL_1 (0)
373 #define FCR_ITL_8 (FCR_ITL1)
374 #define FCR_ITL_16 (FCR_ITL2)
375 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
377 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
378 #define LCR_SB (1 << 6) /* Set Break */
379 #define LCR_STKYP (1 << 5) /* Sticky Parity */
380 #define LCR_EPS (1 << 4) /* Even Parity Select */
381 #define LCR_PEN (1 << 3) /* Parity Enable */
382 #define LCR_STB (1 << 2) /* Stop Bit */
383 #define LCR_WLS1 (1 << 1) /* Word Length Select */
384 #define LCR_WLS0 (1 << 0) /* Word Length Select */
386 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
387 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
388 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
389 #define LSR_BI (1 << 4) /* Break Interrupt */
390 #define LSR_FE (1 << 3) /* Framing Error */
391 #define LSR_PE (1 << 2) /* Parity Error */
392 #define LSR_OE (1 << 1) /* Overrun Error */
393 #define LSR_DR (1 << 0) /* Data Ready */
395 #define MCR_LOOP (1 << 4)
396 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
397 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
398 #define MCR_RTS (1 << 1) /* Request to Send */
399 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
401 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
402 #define MSR_RI (1 << 6) /* Ring Indicator */
403 #define MSR_DSR (1 << 5) /* Data Set Ready */
404 #define MSR_CTS (1 << 4) /* Clear To Send */
405 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
406 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
407 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
408 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
411 * IrSR (Infrared Selection Register)
413 #define STISR_RXPL (1 << 4) /* Receive Data Polarity */
414 #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
415 #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
416 #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
417 #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
424 #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
425 #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
426 #define ICR __REG(0x40301690) /* I2C Control Register - ICR */
427 #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
428 #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
430 #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
431 #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
432 #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
433 #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
434 #define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
436 #define ICR_START (1 << 0) /* start bit */
437 #define ICR_STOP (1 << 1) /* stop bit */
438 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
439 #define ICR_TB (1 << 3) /* transfer byte bit */
440 #define ICR_MA (1 << 4) /* master abort */
441 #define ICR_SCLE (1 << 5) /* master clock enable */
442 #define ICR_IUE (1 << 6) /* unit enable */
443 #define ICR_GCD (1 << 7) /* general call disable */
444 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
445 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
446 #define ICR_BEIE (1 << 10) /* enable bus error ints */
447 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
448 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
449 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
450 #define ICR_UR (1 << 14) /* unit reset */
452 #define ISR_RWM (1 << 0) /* read/write mode */
453 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
454 #define ISR_UB (1 << 2) /* unit busy */
455 #define ISR_IBB (1 << 3) /* bus busy */
456 #define ISR_SSD (1 << 4) /* slave stop detected */
457 #define ISR_ALD (1 << 5) /* arbitration loss detected */
458 #define ISR_ITE (1 << 6) /* tx buffer empty */
459 #define ISR_IRF (1 << 7) /* rx buffer full */
460 #define ISR_GCAD (1 << 8) /* general call address detected */
461 #define ISR_SAD (1 << 9) /* slave address detected */
462 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
466 * Serial Audio Controller
469 #define SACR0 __REG(0x40400000) /* Global Control Register */
470 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
471 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
472 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
473 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
474 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
475 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
477 #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
478 #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
479 #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
480 #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
481 #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
482 #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
483 #define SACR0_ENB (1 << 0) /* Enable I2S Link */
484 #define SACR1_ENLBF (1 << 5) /* Enable Loopback */
485 #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
486 #define SACR1_DREC (1 << 3) /* Disable Recording Function */
487 #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
489 #define SASR0_I2SOFF (1 << 7) /* Controller Status */
490 #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
491 #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
492 #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
493 #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
494 #define SASR0_BSY (1 << 2) /* I2S Busy */
495 #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
496 #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
498 #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
499 #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
501 #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
502 #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
503 #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
504 #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
507 * AC97 Controller registers
510 #define POCR __REG(0x40500000) /* PCM Out Control Register */
511 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
512 #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
514 #define PICR __REG(0x40500004) /* PCM In Control Register */
515 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
516 #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
518 #define MCCR __REG(0x40500008) /* Mic In Control Register */
519 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
520 #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
522 #define GCR __REG(0x4050000C) /* Global Control Register */
524 #define GCR_CLKBPB (1 << 31) /* Internal clock enable */
526 #define GCR_nDMAEN (1 << 24) /* non DMA Enable */
527 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
528 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
529 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
530 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
531 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
532 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
533 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
534 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
535 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
536 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
538 #define POSR __REG(0x40500010) /* PCM Out Status Register */
539 #define POSR_FIFOE (1 << 4) /* FIFO error */
540 #define POSR_FSR (1 << 2) /* FIFO Service Request */
542 #define PISR __REG(0x40500014) /* PCM In Status Register */
543 #define PISR_FIFOE (1 << 4) /* FIFO error */
544 #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
545 #define PISR_FSR (1 << 2) /* FIFO Service Request */
547 #define MCSR __REG(0x40500018) /* Mic In Status Register */
548 #define MCSR_FIFOE (1 << 4) /* FIFO error */
549 #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
550 #define MCSR_FSR (1 << 2) /* FIFO Service Request */
552 #define GSR __REG(0x4050001C) /* Global Status Register */
553 #define GSR_CDONE (1 << 19) /* Command Done */
554 #define GSR_SDONE (1 << 18) /* Status Done */
555 #define GSR_RDCS (1 << 15) /* Read Completion Status */
556 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
557 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
558 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
559 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
560 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
561 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
562 #define GSR_PCR (1 << 8) /* Primary Codec Ready */
563 #define GSR_MCINT (1 << 7) /* Mic In Interrupt */
564 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
565 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
566 #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
567 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
568 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
569 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
571 #define CAR __REG(0x40500020) /* CODEC Access Register */
572 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */
574 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
575 #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
577 #define MOCR __REG(0x40500100) /* Modem Out Control Register */
578 #define MOCR_FEIE (1 << 3) /* FIFO Error */
579 #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
581 #define MICR __REG(0x40500108) /* Modem In Control Register */
582 #define MICR_FEIE (1 << 3) /* FIFO Error */
583 #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
585 #define MOSR __REG(0x40500110) /* Modem Out Status Register */
586 #define MOSR_FIFOE (1 << 4) /* FIFO error */
587 #define MOSR_FSR (1 << 2) /* FIFO Service Request */
589 #define MISR __REG(0x40500118) /* Modem In Status Register */
590 #define MISR_FIFOE (1 << 4) /* FIFO error */
591 #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
592 #define MISR_FSR (1 << 2) /* FIFO Service Request */
594 #define MODR __REG(0x40500140) /* Modem FIFO Data Register */
596 #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
597 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
598 #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
599 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
603 * USB Device Controller
604 * PXA25x and PXA27x USB device controller registers are different.
606 #if defined(CONFIG_PXA25x)
608 #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
609 #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
610 #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
612 #define UDCCR __REG(0x40600000) /* UDC Control Register */
613 #define UDCCR_UDE (1 << 0) /* UDC enable */
614 #define UDCCR_UDA (1 << 1) /* UDC active */
615 #define UDCCR_RSM (1 << 2) /* Device resume */
616 #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
617 #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
618 #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
619 #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
620 #define UDCCR_REM (1 << 7) /* Reset interrupt mask */
622 #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
623 #define UDCCS0_OPR (1 << 0) /* OUT packet ready */
624 #define UDCCS0_IPR (1 << 1) /* IN packet ready */
625 #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
626 #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
627 #define UDCCS0_SST (1 << 4) /* Sent stall */
628 #define UDCCS0_FST (1 << 5) /* Force stall */
629 #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
630 #define UDCCS0_SA (1 << 7) /* Setup active */
632 /* Bulk IN - Endpoint 1,6,11 */
633 #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
634 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
635 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
637 #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
638 #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
639 #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
640 #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
641 #define UDCCS_BI_SST (1 << 4) /* Sent stall */
642 #define UDCCS_BI_FST (1 << 5) /* Force stall */
643 #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
645 /* Bulk OUT - Endpoint 2,7,12 */
646 #define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
647 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
648 #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
650 #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
651 #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
652 #define UDCCS_BO_DME (1 << 3) /* DMA enable */
653 #define UDCCS_BO_SST (1 << 4) /* Sent stall */
654 #define UDCCS_BO_FST (1 << 5) /* Force stall */
655 #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
656 #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
658 /* Isochronous IN - Endpoint 3,8,13 */
659 #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
660 #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
661 #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
663 #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
664 #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
665 #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
666 #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
667 #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
669 /* Isochronous OUT - Endpoint 4,9,14 */
670 #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
671 #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
672 #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
674 #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
675 #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
676 #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
677 #define UDCCS_IO_DME (1 << 3) /* DMA enable */
678 #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
679 #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
681 /* Interrupt IN - Endpoint 5,10,15 */
682 #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
683 #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
684 #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
686 #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
687 #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
688 #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
689 #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
690 #define UDCCS_INT_SST (1 << 4) /* Sent stall */
691 #define UDCCS_INT_FST (1 << 5) /* Force stall */
692 #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
694 #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
695 #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
696 #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
697 #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
698 #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
699 #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
700 #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
701 #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
702 #define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
703 #define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
704 #define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
705 #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
706 #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
707 #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
708 #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
709 #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
710 #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
711 #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
712 #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
713 #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
714 #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
715 #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
716 #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
717 #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
719 #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
721 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
722 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
723 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
724 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
725 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
726 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
727 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
728 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
730 #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
732 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
733 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
734 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
735 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
736 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
737 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
738 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
739 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
741 #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
743 #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
744 #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
745 #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
746 #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
747 #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
748 #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
749 #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
750 #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
752 #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
754 #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
755 #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
756 #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
757 #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
758 #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
759 #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
760 #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
761 #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
763 #elif defined(CONFIG_PXA27x)
765 #define UDCCR __REG(0x40600000) /* UDC Control Register */
766 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
767 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
768 Protocol Port Support */
769 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
771 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
773 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
774 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
775 #define UDCCR_ACN_S 11
776 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
777 #define UDCCR_AIN_S 8
778 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
780 #define UDCCR_AAISN_S 5
781 #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
783 #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
785 #define UDCCR_UDR (1 << 2) /* UDC Resume */
786 #define UDCCR_UDA (1 << 1) /* UDC Active */
787 #define UDCCR_UDE (1 << 0) /* UDC Enable */
789 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
790 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
791 #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
792 #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
794 #define UDC_INT_FIFOERROR (0x2)
795 #define UDC_INT_PACKETCMP (0x1)
797 #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
798 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
799 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
800 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
801 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
802 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
804 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
805 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
806 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
807 #define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
808 #define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
809 #define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
810 #define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
811 #define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
813 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
814 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
815 #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
816 #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
817 Rising Edge Interrupt Enable */
818 #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
819 Falling Edge Interrupt Enable */
820 #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
822 #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
824 #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
826 #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
828 #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
830 #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
832 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
833 Edge Interrupt Enable */
834 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
835 Edge Interrupt Enable */
836 #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
838 #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
841 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
843 #define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
844 #define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
845 #define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
846 #define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
847 #define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
848 #define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
849 #define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
850 #define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
851 #define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
852 #define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
853 #define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
854 #define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
855 #define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
856 #define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
858 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
859 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
860 #define UDCCSR0_SA (1 << 7) /* Setup Active */
861 #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
862 #define UDCCSR0_FST (1 << 5) /* Force Stall */
863 #define UDCCSR0_SST (1 << 4) /* Sent Stall */
864 #define UDCCSR0_DME (1 << 3) /* DMA Enable */
865 #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
866 #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
867 #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
869 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
870 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
871 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
872 #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
873 #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
874 #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
875 #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
876 #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
877 #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
878 #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
879 #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
880 #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
881 #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
882 #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
883 #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
884 #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
885 #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
886 #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
887 #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
888 #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
889 #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
890 #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
891 #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
893 #define UDCCSR_DPE (1 << 9) /* Data Packet Error */
894 #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
895 #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
896 #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
897 #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
898 #define UDCCSR_FST (1 << 5) /* Force STALL */
899 #define UDCCSR_SST (1 << 4) /* Sent STALL */
900 #define UDCCSR_DME (1 << 3) /* DMA Enable */
901 #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
902 #define UDCCSR_PC (1 << 1) /* Packet Complete */
903 #define UDCCSR_FS (1 << 0) /* FIFO needs service */
905 #define UDCBCN(x) __REG2(0x40600200, (x)<<2)
906 #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
907 #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
908 #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
909 #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
910 #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
911 #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
912 #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
913 #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
914 #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
915 #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
916 #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
917 #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
918 #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
919 #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
920 #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
921 #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
922 #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
923 #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
924 #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
925 #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
926 #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
927 #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
928 #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
929 #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
931 #define UDCDN(x) __REG2(0x40600300, (x)<<2)
932 #define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
933 #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
934 #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
935 #define UDCDRA __REG(0x40600304) /* Data Register - EPA */
936 #define UDCDRB __REG(0x40600308) /* Data Register - EPB */
937 #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
938 #define UDCDRD __REG(0x40600310) /* Data Register - EPD */
939 #define UDCDRE __REG(0x40600314) /* Data Register - EPE */
940 #define UDCDRF __REG(0x40600318) /* Data Register - EPF */
941 #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
942 #define UDCDRH __REG(0x40600320) /* Data Register - EPH */
943 #define UDCDRI __REG(0x40600324) /* Data Register - EPI */
944 #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
945 #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
946 #define UDCDRL __REG(0x40600330) /* Data Register - EPL */
947 #define UDCDRM __REG(0x40600334) /* Data Register - EPM */
948 #define UDCDRN __REG(0x40600338) /* Data Register - EPN */
949 #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
950 #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
951 #define UDCDRR __REG(0x40600344) /* Data Register - EPR */
952 #define UDCDRS __REG(0x40600348) /* Data Register - EPS */
953 #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
954 #define UDCDRU __REG(0x40600350) /* Data Register - EPU */
955 #define UDCDRV __REG(0x40600354) /* Data Register - EPV */
956 #define UDCDRW __REG(0x40600358) /* Data Register - EPW */
957 #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
959 #define UDCCN(x) __REG2(0x40600400, (x)<<2)
960 #define UDCCRA __REG(0x40600404) /* Configuration register EPA */
961 #define UDCCRB __REG(0x40600408) /* Configuration register EPB */
962 #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
963 #define UDCCRD __REG(0x40600410) /* Configuration register EPD */
964 #define UDCCRE __REG(0x40600414) /* Configuration register EPE */
965 #define UDCCRF __REG(0x40600418) /* Configuration register EPF */
966 #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
967 #define UDCCRH __REG(0x40600420) /* Configuration register EPH */
968 #define UDCCRI __REG(0x40600424) /* Configuration register EPI */
969 #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
970 #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
971 #define UDCCRL __REG(0x40600430) /* Configuration register EPL */
972 #define UDCCRM __REG(0x40600434) /* Configuration register EPM */
973 #define UDCCRN __REG(0x40600438) /* Configuration register EPN */
974 #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
975 #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
976 #define UDCCRR __REG(0x40600444) /* Configuration register EPR */
977 #define UDCCRS __REG(0x40600448) /* Configuration register EPS */
978 #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
979 #define UDCCRU __REG(0x40600450) /* Configuration register EPU */
980 #define UDCCRV __REG(0x40600454) /* Configuration register EPV */
981 #define UDCCRW __REG(0x40600458) /* Configuration register EPW */
982 #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
984 #define UDCCONR_CN (0x03 << 25) /* Configuration Number */
985 #define UDCCONR_CN_S (25)
986 #define UDCCONR_IN (0x07 << 22) /* Interface Number */
987 #define UDCCONR_IN_S (22)
988 #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
989 #define UDCCONR_AISN_S (19)
990 #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
991 #define UDCCONR_EN_S (15)
992 #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
993 #define UDCCONR_ET_S (13)
994 #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
995 #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
996 #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
997 #define UDCCONR_ET_NU (0x00 << 13) /* Not used */
998 #define UDCCONR_ED (1 << 12) /* Endpoint Direction */
999 #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
1000 #define UDCCONR_MPS_S (2)
1001 #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
1002 #define UDCCONR_EE (1 << 0) /* Endpoint Enable */
1005 #define UDC_INT_FIFOERROR (0x2)
1006 #define UDC_INT_PACKETCMP (0x1)
1008 #define UDC_FNR_MASK (0x7ff)
1010 #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
1011 #define UDC_BCR_MASK (0x3ff)
1015 * Fast Infrared Communication Port
1018 #define FICP __REG(0x40800000) /* Start of FICP area */
1019 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
1020 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
1021 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
1022 #define ICDR __REG(0x4080000c) /* ICP Data Register */
1023 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
1024 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
1026 #define ICCR0_AME (1 << 7) /* Address match enable */
1027 #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
1028 #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
1029 #define ICCR0_RXE (1 << 4) /* Receive enable */
1030 #define ICCR0_TXE (1 << 3) /* Transmit enable */
1031 #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
1032 #define ICCR0_LBM (1 << 1) /* Loopback mode */
1033 #define ICCR0_ITR (1 << 0) /* IrDA transmission */
1035 #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
1036 #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
1037 #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
1038 #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
1039 #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
1040 #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
1042 #ifdef CONFIG_PXA27x
1043 #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
1045 #define ICSR0_FRE (1 << 5) /* Framing error */
1046 #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
1047 #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
1048 #define ICSR0_RAB (1 << 2) /* Receiver abort */
1049 #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
1050 #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
1052 #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
1053 #define ICSR1_CRE (1 << 5) /* CRC error */
1054 #define ICSR1_EOF (1 << 4) /* End of frame */
1055 #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
1056 #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
1057 #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
1058 #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
1065 #define RCNR __REG(0x40900000) /* RTC Count Register */
1066 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
1067 #define RTSR __REG(0x40900008) /* RTC Status Register */
1068 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
1069 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
1071 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
1072 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
1073 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
1074 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
1075 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
1076 #define RTSR_AL (1 << 0) /* RTC alarm detected */
1080 * OS Timer & Match Registers
1083 #define OSMR0 __REG(0x40A00000) /* */
1084 #define OSMR1 __REG(0x40A00004) /* */
1085 #define OSMR2 __REG(0x40A00008) /* */
1086 #define OSMR3 __REG(0x40A0000C) /* */
1087 #define OSMR4 __REG(0x40A00080) /* */
1088 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
1089 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
1090 #define OMCR4 __REG(0x40A000C0) /* */
1091 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
1092 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
1093 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
1095 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
1096 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
1097 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
1098 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
1100 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
1102 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
1103 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
1104 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
1105 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
1109 * Pulse Width Modulator
1112 #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
1113 #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
1114 #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
1116 #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
1117 #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
1118 #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
1122 * Interrupt Controller
1125 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
1126 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
1127 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
1128 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
1129 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
1130 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
1132 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
1133 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
1134 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
1135 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
1136 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
1139 * General Purpose I/O
1142 #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
1143 #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
1144 #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
1145 #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
1147 #define GPLR_OFFSET 0x00
1148 #define GPDR_OFFSET 0x0C
1149 #define GPSR_OFFSET 0x18
1150 #define GPCR_OFFSET 0x24
1151 #define GRER_OFFSET 0x30
1152 #define GFER_OFFSET 0x3C
1153 #define GEDR_OFFSET 0x48
1155 #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
1156 #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
1157 #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
1159 #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
1160 #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
1161 #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
1163 #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
1164 #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
1165 #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
1167 #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
1168 #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
1169 #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
1171 #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1172 #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1173 #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1175 #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1176 #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1177 #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1179 #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
1180 #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
1181 #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
1183 #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
1184 #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
1185 #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
1186 #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
1187 #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
1188 #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
1189 #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
1190 #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
1192 #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
1193 #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
1194 #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
1195 #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
1196 #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1197 #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1198 #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
1200 /* More handy macros. The argument is a literal GPIO number. */
1202 #define GPIO_bit(x) (1 << ((x) & 0x1f))
1204 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1206 /* Interrupt Controller */
1208 #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1209 #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1210 #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1211 #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1212 #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1213 #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1214 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1215 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1217 #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
1218 #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
1219 #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
1220 #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
1221 #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
1222 #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
1223 #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
1224 #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
1225 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
1228 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1229 #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1230 #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1231 #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1232 #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1233 #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1234 #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1235 #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1243 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1244 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1245 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1246 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1247 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1248 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1249 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1250 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1251 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1252 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1253 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1254 #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1255 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1257 #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1258 #define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
1259 #define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
1260 #define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
1261 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1262 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1263 #define PCMD(x) __REG2(0x40F00080, (x)<<2)
1264 #define PCMD0 __REG(0x40F00080 + 0 * 4)
1265 #define PCMD1 __REG(0x40F00080 + 1 * 4)
1266 #define PCMD2 __REG(0x40F00080 + 2 * 4)
1267 #define PCMD3 __REG(0x40F00080 + 3 * 4)
1268 #define PCMD4 __REG(0x40F00080 + 4 * 4)
1269 #define PCMD5 __REG(0x40F00080 + 5 * 4)
1270 #define PCMD6 __REG(0x40F00080 + 6 * 4)
1271 #define PCMD7 __REG(0x40F00080 + 7 * 4)
1272 #define PCMD8 __REG(0x40F00080 + 8 * 4)
1273 #define PCMD9 __REG(0x40F00080 + 9 * 4)
1274 #define PCMD10 __REG(0x40F00080 + 10 * 4)
1275 #define PCMD11 __REG(0x40F00080 + 11 * 4)
1276 #define PCMD12 __REG(0x40F00080 + 12 * 4)
1277 #define PCMD13 __REG(0x40F00080 + 13 * 4)
1278 #define PCMD14 __REG(0x40F00080 + 14 * 4)
1279 #define PCMD15 __REG(0x40F00080 + 15 * 4)
1280 #define PCMD16 __REG(0x40F00080 + 16 * 4)
1281 #define PCMD17 __REG(0x40F00080 + 17 * 4)
1282 #define PCMD18 __REG(0x40F00080 + 18 * 4)
1283 #define PCMD19 __REG(0x40F00080 + 19 * 4)
1284 #define PCMD20 __REG(0x40F00080 + 20 * 4)
1285 #define PCMD21 __REG(0x40F00080 + 21 * 4)
1286 #define PCMD22 __REG(0x40F00080 + 22 * 4)
1287 #define PCMD23 __REG(0x40F00080 + 23 * 4)
1288 #define PCMD24 __REG(0x40F00080 + 24 * 4)
1289 #define PCMD25 __REG(0x40F00080 + 25 * 4)
1290 #define PCMD26 __REG(0x40F00080 + 26 * 4)
1291 #define PCMD27 __REG(0x40F00080 + 27 * 4)
1292 #define PCMD28 __REG(0x40F00080 + 28 * 4)
1293 #define PCMD29 __REG(0x40F00080 + 29 * 4)
1294 #define PCMD30 __REG(0x40F00080 + 30 * 4)
1295 #define PCMD31 __REG(0x40F00080 + 31 * 4)
1297 #define PCMD_MBC (1<<12)
1298 #define PCMD_DCE (1<<11)
1299 #define PCMD_LC (1<<10)
1300 /* FIXME: PCMD_SQC need be checked. */
1301 #define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
1302 bit 9 should be 0 all day. */
1303 #define PVCR_VCSA (0x1<<14)
1304 #define PVCR_CommandDelay (0xf80)
1305 #define PCFR_PI2C_EN (0x1 << 6)
1307 #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1308 #define PSSR_RDH (1 << 5) /* Read Disable Hold */
1309 #define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1310 #define PSSR_STS (1 << 3) /* Standby Mode Status */
1311 #define PSSR_VFS (1 << 2) /* VDD Fault Status */
1312 #define PSSR_BFS (1 << 1) /* Battery Fault Status */
1313 #define PSSR_SSS (1 << 0) /* Software Sleep Status */
1315 #define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
1317 #define PCFR_RO (1 << 15) /* RDH Override */
1318 #define PCFR_PO (1 << 14) /* PH Override */
1319 #define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
1320 #define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
1321 #define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
1322 #define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
1323 #define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
1324 #define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
1325 #define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1326 #define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1327 #define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1328 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1330 #define RCSR_GPR (1 << 3) /* GPIO Reset */
1331 #define RCSR_SMR (1 << 2) /* Sleep Mode */
1332 #define RCSR_WDR (1 << 1) /* Watchdog Reset */
1333 #define RCSR_HWR (1 << 0) /* Hardware Reset */
1335 #define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
1336 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1337 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1338 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1339 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1340 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1341 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1342 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1343 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1344 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1345 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1346 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1347 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1348 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1349 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1350 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1351 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1352 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1355 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
1359 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
1366 #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1367 #define CKEN __REG(0x41300004) /* Clock Enable Register */
1368 #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1369 #define CCSR __REG(0x4130000C) /* Core Clock Status Register */
1371 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1372 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1373 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1375 #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
1376 #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
1377 #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
1378 #define CKEN_MEMC (22) /* Memory Controller Clock Enable */
1379 #define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
1380 #define CKEN_IM (20) /* Internal Memory Clock Enable */
1381 #define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
1382 #define CKEN_USIM (18) /* USIM Unit Clock Enable */
1383 #define CKEN_MSL (17) /* MSL Unit Clock Enable */
1384 #define CKEN_LCD (16) /* LCD Unit Clock Enable */
1385 #define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
1386 #define CKEN_I2C (14) /* I2C Unit Clock Enable */
1387 #define CKEN_FICP (13) /* FICP Unit Clock Enable */
1388 #define CKEN_MMC (12) /* MMC Unit Clock Enable */
1389 #define CKEN_USB (11) /* USB Unit Clock Enable */
1390 #define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
1391 #define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
1392 #define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
1393 #define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
1394 #define CKEN_I2S (8) /* I2S Unit Clock Enable */
1395 #define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
1396 #define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
1397 #define CKEN_STUART (5) /* STUART Unit Clock Enable */
1398 #define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
1399 #define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
1400 #define CKEN_SSP (3) /* SSP Unit Clock Enable */
1401 #define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
1402 #define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
1403 #define CKEN_PWM1 (1) /* PWM1 Clock Enable */
1404 #define CKEN_PWM0 (0) /* PWM0 Clock Enable */
1406 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1407 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1414 #define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
1415 #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
1416 #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
1417 #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
1418 #define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 3 */
1419 #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1420 #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1421 #define LCSR __REG(0x44000038) /* LCD Controller Status Register */
1422 #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
1423 #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
1424 #define TMEDCR __REG(0x44000044) /* TMED Control Register */
1426 #define LCCR3_1BPP (0 << 24)
1427 #define LCCR3_2BPP (1 << 24)
1428 #define LCCR3_4BPP (2 << 24)
1429 #define LCCR3_8BPP (3 << 24)
1430 #define LCCR3_16BPP (4 << 24)
1432 #define LCCR3_PDFOR_0 (0 << 30)
1433 #define LCCR3_PDFOR_1 (1 << 30)
1434 #define LCCR3_PDFOR_2 (2 << 30)
1435 #define LCCR3_PDFOR_3 (3 << 30)
1437 #define LCCR4_PAL_FOR_0 (0 << 15)
1438 #define LCCR4_PAL_FOR_1 (1 << 15)
1439 #define LCCR4_PAL_FOR_2 (2 << 15)
1440 #define LCCR4_PAL_FOR_MASK (3 << 15)
1442 #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1443 #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1444 #define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
1445 #define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
1446 #define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
1447 #define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
1448 #define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
1449 #define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
1451 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
1452 #define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
1453 #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
1454 #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
1455 #define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */
1457 #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
1458 #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
1460 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
1461 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
1462 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
1463 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
1464 #define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
1465 #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
1466 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
1467 #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */
1469 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
1471 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
1473 #define LCCR0_DIS (1 << 10) /* LCD Disable */
1474 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
1475 #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
1476 #define LCCR0_PDD_S 12
1477 #define LCCR0_BM (1 << 20) /* Branch mask */
1478 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
1479 #define LCCR0_LCDT (1 << 22) /* LCD panel type */
1480 #define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
1481 #define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
1482 #define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
1483 #define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
1485 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
1486 #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
1487 (((Pixel) - 1) << FShft (LCCR1_PPL))
1489 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
1490 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
1491 /* pulse Width [1..64 Tpix] */ \
1492 (((Tpix) - 1) << FShft (LCCR1_HSW))
1494 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1495 /* count - 1 [Tpix] */
1496 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
1497 /* [1..256 Tpix] */ \
1498 (((Tpix) - 1) << FShft (LCCR1_ELW))
1500 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1501 /* Wait count - 1 [Tpix] */
1502 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
1503 /* [1..256 Tpix] */ \
1504 (((Tpix) - 1) << FShft (LCCR1_BLW))
1507 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1508 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
1509 (((Line) - 1) << FShft (LCCR2_LPP))
1511 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
1512 /* Width - 1 [Tln] (L_FCLK) */
1513 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
1514 /* Width [1..64 Tln] */ \
1515 (((Tln) - 1) << FShft (LCCR2_VSW))
1517 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1519 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
1520 /* [0..255 Tln] */ \
1521 ((Tln) << FShft (LCCR2_EFW))
1523 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1524 /* Wait count [Tln] */
1525 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
1526 /* [0..255 Tln] */ \
1527 ((Tln) << FShft (LCCR2_BFW))
1530 #define LCCR3_PCD (0xff) /* Pixel clock divisor */
1531 #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
1532 #define LCCR3_ACB_S 8
1535 #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
1536 #define LCCR3_API_S 16
1537 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */
1538 #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
1539 #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
1540 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
1541 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
1543 #define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */
1544 /* active display mode) */
1545 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
1546 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
1549 #define LCCR3_BPP (7 << 24) /* bits per pixel */
1550 #define LCCR3_BPP_S 24
1552 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
1555 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
1556 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
1557 (((Div) << FShft (LCCR3_PCD)))
1560 #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
1561 #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
1562 (((Bpp) << FShft (LCCR3_BPP)))
1564 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
1565 #define LCCR3_Acb(Acb) /* BAC Bias */ \
1566 (((Acb) << FShft (LCCR3_ACB)))
1568 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
1569 /* pulse active High */
1570 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
1572 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
1574 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
1577 #define LCSR_LDD (1 << 0) /* LCD Disable Done */
1578 #define LCSR_SOF (1 << 1) /* Start of frame */
1579 #define LCSR_BER (1 << 2) /* Bus error */
1580 #define LCSR_ABC (1 << 3) /* AC Bias count */
1581 #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1582 #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1583 #define LCSR_OU (1 << 6) /* output FIFO underrun */
1584 #define LCSR_QD (1 << 7) /* quick disable */
1585 #define LCSR_EOF (1 << 8) /* end of frame */
1586 #define LCSR_BS (1 << 9) /* branch status */
1587 #define LCSR_SINT (1 << 10) /* subsequent interrupt */
1589 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1591 #define LCSR_LDD (1 << 0) /* LCD Disable Done */
1592 #define LCSR_SOF (1 << 1) /* Start of frame */
1593 #define LCSR_BER (1 << 2) /* Bus error */
1594 #define LCSR_ABC (1 << 3) /* AC Bias count */
1595 #define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1596 #define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1597 #define LCSR_OU (1 << 6) /* output FIFO underrun */
1598 #define LCSR_QD (1 << 7) /* quick disable */
1599 #define LCSR_EOF (1 << 8) /* end of frame */
1600 #define LCSR_BS (1 << 9) /* branch status */
1601 #define LCSR_SINT (1 << 10) /* subsequent interrupt */
1603 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1605 #ifdef CONFIG_PXA27x
1607 /* Camera Interface */
1608 #define CICR0 __REG(0x50000000)
1609 #define CICR1 __REG(0x50000004)
1610 #define CICR2 __REG(0x50000008)
1611 #define CICR3 __REG(0x5000000C)
1612 #define CICR4 __REG(0x50000010)
1613 #define CISR __REG(0x50000014)
1614 #define CIFR __REG(0x50000018)
1615 #define CITOR __REG(0x5000001C)
1616 #define CIBR0 __REG(0x50000028)
1617 #define CIBR1 __REG(0x50000030)
1618 #define CIBR2 __REG(0x50000038)
1620 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
1621 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
1622 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
1623 #define CICR0_ENB (1 << 28) /* Camera interface enable */
1624 #define CICR0_DIS (1 << 27) /* Camera interface disable */
1625 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
1626 #define CICR0_TOM (1 << 9) /* Time-out mask */
1627 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
1628 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
1629 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
1630 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
1631 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
1632 #define CICR0_CDM (1 << 3) /* Disable-done mask */
1633 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
1634 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
1635 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
1637 #define CICR1_TBIT (1 << 31) /* Transparency bit */
1638 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
1639 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
1640 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
1641 #define CICR1_RGB_F (1 << 11) /* RGB format */
1642 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
1643 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
1644 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
1645 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
1646 #define CICR1_DW (0x7 << 0) /* Data width mask */
1648 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
1650 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
1652 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
1653 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
1655 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
1658 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
1660 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
1662 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
1663 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
1665 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
1667 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
1668 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
1669 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
1670 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
1671 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
1672 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
1673 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
1674 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
1676 #define CISR_FTO (1 << 15) /* FIFO time-out */
1677 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
1678 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
1679 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
1680 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
1681 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
1682 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
1683 #define CISR_EOL (1 << 8) /* End of line */
1684 #define CISR_PAR_ERR (1 << 7) /* Parity error */
1685 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
1686 #define CISR_CDD (1 << 5) /* Camera interface disable done */
1687 #define CISR_SOF (1 << 4) /* Start of frame */
1688 #define CISR_EOF (1 << 3) /* End of frame */
1689 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
1690 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
1691 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
1693 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
1694 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
1695 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
1696 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
1697 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
1698 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
1699 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
1700 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
1702 #define SRAM_SIZE 0x40000 /* 4x64K */
1704 #define SRAM_MEM_PHYS 0x5C000000
1706 #define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
1707 #define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
1709 #define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
1710 #define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
1711 #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
1712 #define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
1714 #define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
1715 #define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
1716 #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
1717 #define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
1719 #define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
1720 #define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
1721 #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
1722 #define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
1724 #define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
1725 #define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
1726 #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
1727 #define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
1729 #define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
1730 #define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
1731 #define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
1732 #define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
1734 #define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
1736 #define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
1737 #define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
1738 #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
1740 #define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
1741 #define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
1742 #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
1744 #define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
1745 #define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
1746 #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
1748 #define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
1749 #define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
1750 #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
1754 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1756 * UHC: USB Host Controller (OHCI-like) register definitions
1758 #define UHC_BASE_PHYS (0x4C000000)
1759 #define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
1760 #define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
1761 #define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
1762 #define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
1763 #define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
1764 #define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
1765 #define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
1766 #define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
1767 #define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
1768 #define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
1769 #define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
1770 #define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
1771 #define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
1772 #define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
1773 #define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
1774 #define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
1775 #define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
1776 #define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
1778 #define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
1779 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
1781 #define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
1782 #define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
1783 #define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
1784 #define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
1785 #define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
1787 #define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
1788 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
1789 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
1790 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
1791 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
1792 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
1793 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
1794 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
1795 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
1796 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
1798 #define UHCHR __REG(0x4C000064) /* UHC Reset Register */
1799 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
1800 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
1801 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
1802 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
1803 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
1804 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
1805 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
1806 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
1807 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
1808 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
1809 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
1811 #define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
1812 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
1813 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
1814 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
1815 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
1816 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
1818 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
1819 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
1821 #define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
1823 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
1825 /* PWRMODE register M field values */
1827 #define PWRMODE_IDLE 0x1
1828 #define PWRMODE_STANDBY 0x2
1829 #define PWRMODE_SLEEP 0x3
1830 #define PWRMODE_DEEPSLEEP 0x7
projects / linux-2.6 / blob