2 * include/asm-arm/arch-lh7a40x/entry-macro.S
4 * Low-level IRQ helper macros for LH7A40x platforms
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
10 #include <asm/hardware.h>
11 #include <asm/arch/irqs.h>
13 /* In order to allow there to be support for both of the processor
14 classes at the same time, we make a hack here that isn't very
15 pretty. At startup, the link pointed to with the
16 branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
17 detected as a lh7a404.
19 *** FIXME: we should clean this up so that there is only one
20 implementation for each CPU's design.
24 #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
29 .macro get_irqnr_preamble, base, tmp
32 .macro arch_ret_to_user, tmp1, tmp2
35 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
37 branch_irq_lh7a400: b 1000f
39 @ Implementation of the LH7A404 get_irqnr_and_base.
41 mov \irqnr, #0 @ VIC1 irq base
42 mov \base, #io_p2v(0x80000000) @ APB registers
43 add \base, \base, #0x8000
44 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
45 tst \tmp, #VA_VECTORED @ Direct vectored
47 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
48 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
50 add \base, \base, #(0xa000 - 0x8000)
51 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
52 tst \tmp, #VA_VECTORED @ Direct vectored
54 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
55 mov \irqnr, #32 @ VIC2 irq base
57 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
58 bcs 1008f @ Bit set; irq found
59 add \irqnr, \irqnr, #1
60 bne 1001b @ Until no bits
61 b 1009f @ Nothing? Hmm.
62 1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
63 1008: movs \irqstat, #1 @ Force !Z
64 str \tmp, [\base, #0x0030] @ Clear vector
67 @ Implementation of the LH7A400 get_irqnr_and_base.
70 mov \base, #io_p2v(0x80000000) @ APB registers
71 ldr \irqstat, [\base, #0x500] @ PIC INTSR
73 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
74 bcs 1008f @ Bit set; irq found
75 add \irqnr, \irqnr, #1
76 bne 1001b @ Until no bits
77 b 1009f @ Nothing? Hmm.
78 1008: movs \irqstat, #1 @ Force !Z
85 #elif defined (CONFIG_ARCH_LH7A400)
89 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
91 mov \base, #io_p2v(0x80000000) @ APB registers
92 ldr \irqstat, [\base, #0x500] @ PIC INTSR
94 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
95 bcs 1008f @ Bit set; irq found
96 add \irqnr, \irqnr, #1
97 bne 1001b @ Until no bits
98 b 1009f @ Nothing? Hmm.
99 1008: movs \irqstat, #1 @ Force !Z
103 #elif defined(CONFIG_ARCH_LH7A404)
108 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
109 mov \irqnr, #0 @ VIC1 irq base
110 mov \base, #io_p2v(0x80000000) @ APB registers
111 add \base, \base, #0x8000
112 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
113 tst \tmp, #VA_VECTORED @ Direct vectored
115 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
116 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
118 add \base, \base, #(0xa000 - 0x8000)
119 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
120 tst \tmp, #VA_VECTORED @ Direct vectored
122 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
123 mov \irqnr, #32 @ VIC2 irq base
125 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
126 bcs 1008f @ Bit set; irq found
127 add \irqnr, \irqnr, #1
128 bne 1001b @ Until no bits
129 b 1009f @ Nothing? Hmm.
130 1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
131 1008: movs \irqstat, #1 @ Force !Z
132 str \tmp, [\base, #0x0030] @ Clear vector